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2015-06-05AMD K8 fam10: Drop extra HT scan_chain() parametersKyösti Mälkki
Change-Id: Ice7cb89c19585cf725b6f73c33443050f8d65418 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8565 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Drop local is_sblink in scan_chainsKyösti Mälkki
We can define is_sblink = (max == 0) as sblink is always the very first chain we scan. Change-Id: Ibd6b3ea23954ca919ae148604bca2495e9f8753b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8564 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Drop redundant parameters on scan_chain()Kyösti Mälkki
Change-Id: I6041b666e6792cf97b8273ed54832d86af8ed23e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8563 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor HT link connection testKyösti Mälkki
Change-Id: I1e935a6b848a59f7f2e58779bceea599032de9e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8562 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
Change-Id: I65fad1cfba95f0ee1ed3f7f7a57d874144da1e40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8561 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Relocate SB_HT_CHAIN in devicetreeKyösti Mälkki
When we want to scan the HT chain to southbridge first, we relocate it as the first item of dev->link_list of node 0. Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8560 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0Kyösti Mälkki
Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8353 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8365 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8: Refactor calls for HT configurationKyösti Mälkki
Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8559 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD fam10: Refactor calls for HT configurationKyösti Mälkki
Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8558 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05devicetree: Add fields for HyperTransport scansKyösti Mälkki
Change-Id: I3b00e5e4e45089fbd7d0d6243d5e441bd8929c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8557 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Eliminate local variable min_busKyösti Mälkki
Some cases of max==0xff wrapping around the 8-bit link->secondary register remain to be solved. Change-Id: I01e2ab6b2f23a03dbac49207ab584eccd1ca9b1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8364 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8352 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Eliminate local variables busn and max_busKyösti Mälkki
Change-Id: I297de09dcf93511acece4441593ef958a390fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8362 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Add ht_route_link()Kyösti Mälkki
Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8556 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD fam10: Fix add_more_linksKyösti Mälkki
One PCI function may contain upto 4 links, further links must be added to PCI function 4 on the same device. There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8555 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04build system: move more clang handling to xcompilePatrick Georgi
clang requires some additional options to disable warnings which can be handled by xcompile. Also drop the hard coded clang compilers in Makefile Change-Id: I0f12f755420f315127e6d9adc00b1246c6e7131b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7612 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04arch/x86: No need to specify -Wa,--divide in a MakefilePatrick Georgi
We test for it in xcompile and add it to CFLAGS. Change-Id: I041a881b542bc55c1725af384f038da3356e3bb1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04build system: move compiler runtime determination to xcompilePatrick Georgi
Instead of fetching libgcc's location and required compiler flags on every individual build, do it once in xcompile. Change-Id: Ie5832fcb21710c4cf381ba475589d42ce0235f96 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/10425 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-04xcompile: Detect clang compilersPatrick Georgi
This uses the availability of CONFIG_* variables in .xcompile and tests for compilers in xcompile so that the build system doesn't need to probe them. Change-Id: I359ad6245d2527efa7e848a9b38f5f194744c827 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/10424 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04xcompile: Rename internal variable CFLAGS to CFLAGS_GCCPatrick Georgi
This is in preparation of adding support for clang to xcompile. Change-Id: I518d077f134610082b0939b1525682f2289eec34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10423 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04board_id: Remove extra quotes.Vladimir Serbinenko
Kconfig already quotes the string. Double quoting actually removes the quoting. Change-Id: I927d90dc2ce8af4e8d2d700d2bb3e04254459e1b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10382 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04build system: Move .xcompile include further downPatrick Georgi
It's not used until then, but by moving it below including .config, we can use CONFIG_* in the .xcompile file in the future. Change-Id: I672f444dd28b5fae1fc339a1e0e78a249c9b7875 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10422 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-04crossgcc: Improve compatibility of the toolchain across host systemsPatrick Georgi
crossgcc builds gmp, whose build system normally optimises for the hardware it's built on. That may give a minor performance boost but has the downside that the compiler becomes non-portable and may break on other systems due to illegal instructions. Setting CFLAGS to some reasonable value prevents gmp's configure script from choosing CPU specific -mtune flags (which may enable optimizations that only run on CPUs with the same feature set). Enabling "fat" builds make the build system add all optimized assembler routines and makes the selection of the right one a runtime decision instead of deciding at compile time. Change-Id: I72d20627270baa082cd02ebb4c9a09cd23f30f8c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10412 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04devicetree: Change scan_bus() prototype in device opsKyösti Mälkki
The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04devicetree: Single scan_bridges()Kyösti Mälkki
Change-Id: Ifd277992a69a4182e2fac92aaf746abe4fec2a1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8540 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04PCI subsystem: Drop parameter max from scan_busKyösti Mälkki
Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04PCI subsystem: Use subordinate property to track bus enumerationKyösti Mälkki
Parameter max is the cumulative number of PCI buses scanned on the system so far. Use the property subordinate from the parent PCI bridge device to keep track of the first available bus number instead of passing that on the stack. Change-Id: I1a884c98d50fa4f1eb2752e10b778aea8a7b090a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8537 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04PCI subsystem: Refactor PCI bridge register controlKyösti Mälkki
Change-Id: I1766c92abe7a74326c49df74ba38930a502fcb5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8536 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04devicetree: Rename unused parameter max in domain_scan_bus()Kyösti Mälkki
For the PCI root node, input parameter max==0 and output value max is not relevant for operation. Change-Id: I23adab24aa957c4d51d703098a9a40ed660b4e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8855 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04devicetree: Rename unused parameter to passthruKyösti Mälkki
The actual use of the parameter max is to keep track of PCI bus number while recursively scanning PCI bridges or PCI-e rootports. Neither CPU, SMBus, LPC or other static buses are involved in this enumeration, but the way bridge operations were originally designed forced to pass this argument thru unrelated functions. Follow-up removes these once the function prototype gets fixed. Change-Id: Idbc9c515a362c571a1798bb36972058b309c2774 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8535 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04HyperTransport: Use subordinate property to track chain enumerationKyösti Mälkki
For amdfam10, (ht_c_index > 3) never evaluates true as the code already has a return for this case above. Change-Id: Ie90941671e1b2b4f42e2b1b0641ca59334fcf0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8688 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04HyperTransport: Move pci_scan_bus() callKyösti Mälkki
Allows to remove parameter max from the call, it is not involved with the unitid assignment. Change-Id: I087622f4ff69474f0b27cfd8709106ab8ac4ca98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8687 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Idcd059f05523916f726b94931c2487ab028b7d72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10409 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-03libpayload: usb: Support MTK xHCI host controllerYidi Lin
1. There is a mis-understanding to calculate the value of TD Size in Normal TRB. For MTK's xHCI controller it defines a number of packets that remain to be transferred for a TD after processing all Max packets in all previous TRBs, that means don't include the current TRB's. 2. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK architecture defines some extra SW scheduling parameters for HW. According to these parameters provided by SW, the xHC can easily decide whether a synchronous endpoint should be scheduled in a specific uFrame. The extra SW scheduling parameters are put into reserved DWs in Slot and Endpoint Context. But in coreboot synchronous transfer can be ignored, so only two fields are set to a default value 1 to support bulk and interrupt transfers, and others are set to zero. 3. For control transfer, it is better to read back doorbell register or add a memory barrier after ringing the doorbell to flush posted write. Otherwise the first command will be aborted on MTK's xHCI controller. 4. Before send commands to a port, the Port Power in PORTSC register should be set to 1 on MTK's xHCI so a hook function of enable_port in generic_hub_ops_t struct is provided. Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41 Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265362 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10389 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-03libpayload: usb: Max packet size of SuperSpeed control EPs should be 512.Chunfeng Yun
BRANCH=none BUG=none TEST=none Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409 Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269863 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-02cbfs: Fix mismerge.Vladimir Serbinenko
cbfs_get_file_content was replaced with cbfs_boot_map_with_leak but 36f8d27ea9f741e184b76b5f42d7f777f207edc0 failed to get it into account. Change-Id: I0c7840043b2ea6abaf8e70f4bf1a63c96aedebc1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10403 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02tpm: Add dummy _DSM to make Bitlocker happy.Vladimir Serbinenko
Change-Id: Ieb6f70f5b2863336bd6143b2dfbb1d67c4c26109 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02Make DSDT a file in CBFS rather than embedding it into ramstage.Vladimir Serbinenko
Makes it cleaner by putting AML into separate file rather than having an array in C code. Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02Hide PLATFORM_USES_FSP1_1.Vladimir Serbinenko
This should be an internal selectable variable rather than user-visible config. Moreover the description is misleading. This is a typical case of an option "Should it work?" where there is only one right answer yet we still ask it. Change-Id: Idc0ce2e1b9f89eddd034966cc877483d994ce0eb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02Kconfig: Remove RELOCATABLE_MODULES.Vladimir Serbinenko
RELOCATABLE_MODULES controls inclusion of rmodule support but including it without having anything that uses it is a pure waste of space. So instead make RELOCATABLE_MODULES be selected exactly when there is something using it. Change-Id: I377a955f0cd95b0f811b986df287864c3dc9f89a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02assets: abstract away the firmware assets used for bootingAaron Durbin
As there can be more than one source of firmware assets this patch generalizes the notion of locating a particular asset. struct asset is added along with some helper functions for working on assets as a first class citizen. Change-Id: I2ce575d1e5259aed4c34c3dcfd438abe9db1d7b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10264 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02prog_loading: add region_device representing memoryAaron Durbin
One can remove the struct buffer_area and use the region_device embedded in the struct prog to represent the in-memory loaded program. Do this by introducing a addrspace_32bit mem_region_device that can have region_device operations performed on it. The addrspace_32bit name was chosen to make it explicit that 32-bits of address space is supported at the max. Change-Id: Ifffa0ef301141de940e54581b5a7b6cd81311ead Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10261 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02x86: fix mirror_payload()Aaron Durbin
The api to mirror_payload() was changed, but as no board in coreboot.org selected MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING this issue was missed. Update to using the prog functions. Change-Id: I4037f5dc6059c0707e1bf38eb1fa3d1bbb408e2a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10260 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02Revert "pistashio: bump up romstage size"Aaron Durbin
This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e. Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10222 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02libpayload: Add div_round_up() functionJulius Werner
The lack of a div_round_up() function in libpayload keeps being a problem for payloads and has already caused us to sprinkle numerous less-readable ALIGN_UP(n, d) / d throughout depthcharge. Let's add this so we can avoid adding any more and then maybe cocchinelle them all over later. BRANCH=None BUG=None TEST=None Change-Id: I241a52770a0edcf7003b48a81875b3fa0cb7ed53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3f9514f9cfd325cc3c4b542020574b605fac935 Original-Change-Id: Ia55bd4bc52ab8a249b4854e40727cf6917af7b30 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273050 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-02ipq806x: clear the RPM initialization Acknowledge bitSourabh Banerjee
The RPM initialization Acknowledge is cleared by writing 1 into bit-10 of the RPM_INT_ACK register. The existing code got it wrong and is writing zero to that bit. BRANCH=storm BUG=chrome-os-partner:39231 TEST=with this patch and an RPM firmware update, an SP4 device survived more than 1000 reboots in a row. Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7 Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524 Original-Signed-off-by: Viswanath Kraleti <vkraleti@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/266969 Original-Reviewed-by: Manoj Juneja <mjuneja@qti.qualcomm.com> Reviewed-on: http://review.coreboot.org/10310 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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