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2013-07-20it8728f: Add ITE IT8728F superio early serial support.Damien Zammit
This is the first of a series of patches to provide support for a new mainboard, Gigabyte GA-B75M-D3V. This patch provides early serial for the superio and has been tested on this mainboard. The code is based on IT8718F superio. Change-Id: I5636199b49314166ed3b81e60b41131964dd44ff Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/3794 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-07-18AMD Yangtze: Update 3rdparty hash for new blobsBruce Griffith
Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-18SMBIOS: Clarify prompts and help texts for Serial and Version NumbersPeter Stuge
Change-Id: If1fa39db79eeecbef90c8695143d2fe2adf2f21a Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3732 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-17Revert "lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String"Peter Stuge
This reverts commit cd24e3f6a7adecfc9d3b2a2dd2f81d84acffa91b. Change-Id: I3d1fec75d99d0b480a47b4d433c14a681831d9f8 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3778 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-07-17lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM StringPeter Stuge
The Linux thinkpad_acpi.c driver looks for this string while reading information about the system it is running on. This commit does not make the module load but it is one of several things that the module looks for on a ThinkPad. The use of 3 defines for the serial number template seems odd but it's done in a way that eliminates magic numbers, yet avoids use of strcpy, strlen, strindex, strchr, or strspan: we can have some correctness assured at compile time. Also, the defines can be copy/pasted for other mainboards and we should void errors due to people not changing magic numbers. Change-Id: Ief5f28d2e27bf959cb579c4c8eea9eecc9a89a7c Signed-off-by: Peter Stuge <peter@stuge.se> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-16beaglebone: Get rid of a redundant CBFS_ROM_OFFSET.Gabe Black
CBFS_ROM_OFFSET was declared in both the am335x config and the beaglebone config. This removes it from the beaglebone config. Change-Id: I657cb8e83a1ee961d8bdc995a41f303920bc53f9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-07-16AMD Fam15tn: Split DSDT into common sectionsSteve Goodrich
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/3629 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-15CBFS: Use memmove instead of memcpy when loading a file from CBFS.Gabe Black
It might be the case that a file is being loaded from a portion of CBFS which has already been loaded into a limitted bit of memory somewhere, and we want to load that file in place, effectively, so that it's original location in CBFS overlaps with its new location. That's only guaranteed to work if you use memmove instead of memcpy. Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3577 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-15am335x: Make the default media for the bootblock sram instead of NAND flash.Gabe Black
The SOC's built in ROM loads the bootblock and the ROM stage into the on chip memory before handing over control to the bootblock. To avoid having to add one or more driver to the bootblock so that it can re-load the ROM stage from whatever media Coreboot is stored on, we can just take advantage of the copy that's already there. Loading the RAM stage/payloads won't be so simple, so the ROM stage and the RAM stage will have to have different media drivers. Change-Id: Id74ed4bc3afd2063277a36e666080522af2305dd Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3583 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig.Gabe Black
This variable wasn't being defined and was defaulting to zero when used in the ROM stage's linker script. This change defines it as a variable, and gives it a value which is slightly beyond the end of the bootblock. By making the ROM stage request to be loaded slightly farther into memory than it was loaded by the SOC's masked ROM, we ensure that it's moved away from the stage's metadata instead of on top of it. When it moves the other way, it clobbers important values like the entry point vefore the bootblock has had a chance to use them. Change-Id: I027a1365d05f1d79d7fc1e1349965ccb7d4e81b9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3582 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15beaglebone: Put some code in romstage.c so we can tell if it ran.Gabe Black
The placeholder code in beaglebone's romstage.c didn't do anything, it just immediately tried to load the RAM stage and jump into it. That doesn't currently work, and there's no indication whether you actually successfully got into the ROM stage or not. This change adds a few lines which initialize the console and say "Hi" so that we can tell that the ROM stage is running. Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15ARM: Define custom ELF headers for ARM.Gabe Black
At least when building with the gnu toolchain, the headers the linker automatically generate save space for the actual ELF headers in one of the loadable segments. This creates two problems. First, the data you intended to be at the start of the image doesn't actually show up there, it's actually the ELF headers. Second, the ELF headers are essentially useless for firmware since there's currently nothing to tell you where they are, and even if there was, there isn't much of a reason to look at them. They're useful in userspace for, for instance, the dynamic linker, but not really in firmware. This change adds a PHDRS construct to each of the linker scripts used on ARM which define a single segment called to_load which does not have the flag set which would tell the linker to put headers in it. The first section defined in the script has ": to_load" to tell the linker which segment to put it in, and from that point on the other sections go in there by default. Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3580 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15SMBIOS: Add smbios_write_type11() for creating an OEM Strings structurePeter Stuge
Change-Id: Id338968429435bac26595c4843b07cdbb91dd64d Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14SMBIOS: Allow overriding default Manufacturer and Product namesPeter Stuge
The vendor and part name from coreboot is normally stored in these SMBIOS structure fields, but it can be useful to override them. On Lenovo ThinkPads an override is e.g. needed to convince the Linux thinkpad_acpi.c driver that it is actually running on a ThinkPad. Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-14lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVOPeter Stuge
This is needed for the Linux thinkpad_acpi.c driver to load. Change-Id: I3d9549395556ffb0abfc3cb52b3d01386c34caa5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3731 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14arm: Add and enable an arch specific version of memmove.Gabe Black
This version is taken from arch/arm/lib/memmove.S in the Linux kernel. Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14x86: Add and enable an arch verson of memmove.Gabe Black
This is from memcpy_32.c in the Linux kernel. There was no copyright header in the original file either. Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3762 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.Gabe Black
Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-13lenovo/x60: Move mainboard_enable() code into a mainboard_init()Peter Stuge
mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: Iaf9187532a1e432b991260201b95dda85cc312c5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-12src/southbridge/intel/{lynxpoint,bd82x6x}/spi.c: correct spelling of attemptedPaul Menzel
Change-Id: Ic6f6af6298fed2f41f140a7aa62dccf98bf60927 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3572 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11cpu: Fix spellingMartin Roth
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11include: Fix spellingMartin Roth
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11usbdebug: Cleanup dbgp_ehci_info callKyösti Mälkki
Change-Id: I9cad64796fcfb7a50d9ed9ec95c56ab855c872e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3766 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11usbdebug: Drop old includesKyösti Mälkki
Change-Id: I4786bff41fef924c72087c354e394bdc1996cadc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11Move the HAVE_ARCH_* config options from src/arch/x86 to src/.Gabe Black
The options that keep track of whether there are arch versions of the standard string functions shouldn't be in the arch/x86 directory since they apply to all architectures. Move them into the higher level, shared Kconfig defaulting to off. Then, in each applicable arch (currently all of them) they can be selected to on. Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11arm: Add a W() macro for use in kernel assembler.Gabe Black
Some kernel assembly code uses a W macro to optionally add a .w to instructions that need to be 32 bit thumb. The gnu assembler doesn't seem to need the .w and won't assemble if it's provided. Change-Id: I0a288177788b5c61810ee7bd3d2debea66835de2 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3759 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11Fix CBMEM console use with CAR_MIGRATIONKyösti Mälkki
With EARLY_CBMEM_INIT and CAR_MIGRATION selected, cbmemc_reinit() was called twice during romstage. This effectively deleted output of romstage in CBMEM console. Change-Id: I21072a319c0e4a5f695b0573bc017bf7921fc663 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11Unify PCI configuration cyclesKyösti Mälkki
Split PCI IO configuration and MMIO configuration cycles to separate files. Modern hardware does not use IO cycles for PCI configuration after initial setup in bootblock. Note that the pci_mmio_ and pcie_ functions were different in masking the alignment for register address. PCI standard requires that 16-bit and 32-bit configuration register writes do not cross boundaries. Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Vortex86EX southbridge routes more built-in PCI device IRQs.Andrew Wu
Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus. Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10usbdebug: Put ehci_debug_info in CAR_GLOBALKyösti Mälkki
Store EHCI Debug Port runtime variables in CAR_GLOBAL. For platforms without CAR_MIGRATION, logging on EHCI Debug Port is temporarily lost when CAR is torn down at end of romstage. On model_2065x and model_206ax ehci_debug_info was overlapping the MRC variable region and additionally migration used incorrect size for the structure. Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3475 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-10usbdebug: Move EHCI BAR relocation codeKyösti Mälkki
There are other uses for EHCI debug port besides console, so move EHCI relocation code from console to lib. Change-Id: I95cddd31be529351d9ec68f14782cc3cbe08c617 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3626 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-10usbdebug: Move ehci_debug_info allocationKyösti Mälkki
Move ehci_debug_info allocation from console to lib, as console code was only built for ramstage. Implement dbgp_ehci_info() to return the EHCI context. Alread alias this as dbgp_console_input() and _output() to return the console stream context later on. Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3625 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10usbdebug: Refactor disable logicKyösti Mälkki
Output to usbdebug console needs to be disabled until hardware is initialized and while EHCI BAR is relocated. Add separate field ehci_info to point to back to EHCI context when hardware is ready to transfer data. Change-Id: If7d441b561819ab8ae23ed9f3f320f7742ed231e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10pit: Redo the display port bridge initialization code.Gabe Black
The display port bridge on pit is different from the one on snow and needs to be initialized differently. Instead of waiting for the chip to come up on its own and assert the hotplug detect, we need to access it over i2c and get it up and running ourselves. Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Enable the ps8625 driver.Gabe Black
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10parade: Add a driver for the parade ps8625.Gabe Black
This driver is basically the same as the one in U-Boot but without the device tree stuff. That driver is, in turn, a straightforward implementation of the sequence of register writes described in the data sheet. Comments were added in U-Boot which helpfully describe what the register writes are actually doing and are kept. Change-Id: I64ba6b373478853bb2120f0553a43de901170d02 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/3753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10i2c: Change the type of the data parameter to uint8_t.Gabe Black
Data is intended to be a byte array, so it should be described by a type which has a fixed size equal to an 8 bit byte. Also, the data passed to write shouldn't be modified and can be const. Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop setting up the hardware dp hotplug detect in ROM stage too.Gabe Black
This was removed from ramstage a little while ago and should have been removed from here as well. Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: add panel to the list of things to be powered up by the PMICRonald G. Minnich
This appears to be needed, though we have no way to test yet. Change-Id: I39033581011e056258193f2cdff78814361a8d55 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos: Prevent unexpected reboots in resume.Hung-Te Lin
In resume path, if memory setup takes too long without setting PS_HOLD, EC watch dog may power off or reboot the system. To prevent that, we should enable PS_HOLD in same timing as cold boot - right before starting memory setup. Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the tps65090 functions and adjust the hotplug detect line.Gabe Black
The functions which manipulated the tps65090 were removed a while ago because it isn't accessible directly from the AP, it's on an I2C bus that has to be accessed by the EC on our behalf. Now that that capability has been added, we can rewrite the small portion of the the tps65090 we actually used but using the EC passthrough commands. Also, we should not be configuring the hardware display port hotplug detect line since we're using it as a GPIO for other purposes. The GPIO we're using instead defaults to being an input, but to be safe we should probably explicitly configure it as one anyway. Change-Id: I7f8a8a767e3cccb813513940a5feceea482982f5 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10chromeec: Add a function to send passthrough i2c messages.Gabe Black
Change-Id: I576d0dbf65693f40d7d1c20d3d5e7a75b8e14dc9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/3752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Correct EC device in mainboard configuration.Hung-Te Lin
The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C. Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Remove the extra reopen when reading SPI.Hung-Te Lin
The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Apply new implementation for SPI transmission.Hung-Te Lin
Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.Hung-Te Lin
The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI open/close/reset procedure.Hung-Te Lin
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Provide configuration for SPI0~SPI2.Hung-Te Lin
Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Change SPI module to standard <spi-generic> interface.Hung-Te Lin
The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard (spi-generic.h) and will be a problem when we want to share SPI drivers. This commit replaces exynos_spi_* by spi_* functions. Note, exynos_spi_read is kept and changed to a static function because its usage is different from the standard API "spi_xfer". Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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