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2016-11-17arch/x86/acpigen: acpigen buffer size fixNaresh G Solanki
In function definition of acpigen_write_byte_buffer, buffer size written using acpigen_emit_byte gives wrong results in generated AML code for buffer size greater than one. Write buffer size using acpigen_write_integer as per ACPI spec 5.0 section 20.2.5.4 BufferOp. Change-Id: I0dcb25b24a1b4b592ad820c95f7c2df67a016594 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17444 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-16drivers/i2c/alps: Add support for ALPS Touchpad driverBarnali Sarkar
Add support for I2C ALPS Touchpad Device Driver. BUG=none BRANCH=none TEST=Build and booted successfully on KBL RVP and Touchpad is working Change-Id: I78b77bd7c4694ccf61260724f593bd59545c70e6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17390 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-16include/device/pci_ids.h: Correct Entertainment sub-classElyes HAOUAS
According to PCI LOCAL BUS SPECIFICATION, REV. 3.0 page 305, the sub-class for Entertainment en/decryption is 0x1010 Change-Id: Ia069e2ec328a8180fc1e2e70146c3710e703ee59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17436 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-16intel/fsp_baytrail: Fix assignment of PcdeMMCBootModeDavid Imhoff
Before the PcdeMMCBootMode in the Updatable Product Date was always assigned and didn't take into account the + 1 increment for the default define. Now if the configuration indicates that the device tree should be followed PcdeMMCBootMode is initially disabled. Else if configuration isn't the default, assign the value with the + 1 increment substracted. TEST=Intel/MinnowMax Change-Id: I6755eb585d1afe3a15f83347fba834766eb44ad2 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: https://review.coreboot.org/10165 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16intel/fsp_baytrail: Always log PcdEnableLpe and PcdeMMCBootModeDavid Imhoff
Log the values of PcdEnableLpe and PcdeMMCBootMode even if they are outside of the expected range. TEST=Intel/MinnowMax Change-Id: Ie0aea4287234b23d4e9852f3991dcc78ce8103d9 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: https://review.coreboot.org/10164 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-16mb/ga-945gcm-s2l: Clean up SuperioArthur Heymans
GPIO register at offset 0xfc (VID Input Register) is read-only but writing 1 to bit 0 will update initial VID input. Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17412 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16google/eve: Fill out memory ID tableDuncan Laurie
Add the DIMM SPD data for memory types that are not used yet but are on the matrix and may be used in future builds. Also fix a typo in the part number string for one type. BUG=chrome-os-partner:58666 TEST=build and boot on eve p0 Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16vboot: make TPM factory init sequence more robust.Vadim Bendebury
Currently the code considers the absence of the NVRAM firmware rollback space a a trigger for invoking the TPM factory initialization sequence. Note that the kernel rollback and MRC cache hash spaces are created after the firmware rollback space. This opens an ever so narrow window of opportunity for bricking the device, in case a startup is interrupted after firmware space has been created, but before kernel and MRC hash spaces are created. The suggested solution is to create the firmware space last, and to allow for kernel and MRC cache spaces to exist during TPM factory initialization. BRANCH=none BUG=chrome-os-partner:59654 TEST=odified the code not to create the firmware space, wiped out the TPM NVRAM and booted the device. Observed it create kernel and MRC cache spaces on the first run, and then reporting return code 0x14c for already existing spaces on the following restarts. Verified that the device boots fine in normal and recovery modes and TPM NVRAM spaces are writeable in recovery mode. Change-Id: Id0e772448d6af1340e800ec3b78ec67913aa6289 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17398 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-16vboot: TPM2 - report attempts to re-create NVRAM spacesVadim Bendebury
Currently the tlcl_define_space() function returns the same error value for any non-zero TPM response code. The thing is that the caller might want to allow attempts to re-create existing NVRAM spaces. This patch adds a new API return value to indicate this condition and uses it as appropriate. BRANCH=none BUG=chrome-os-partner:59654 TEST=for test purposes modified the code not to create the firmware space, wiped out the TPM NVRAM and booted the device. Observed it create kernel and MRC index spaces on the first boot and then reporting return code 0x14c for already existing spaces on the following restarts. Change-Id: Ic183eb45e73edfbccf11cc19fd2f64f64274bfb2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16arch/x86/acpigen: Fix acpigen for If (Lequal (...))Furquan Shaikh
acpigen_write_if_lequal is used to generate ACPI code to check if two operands are equal, where operand1 is an ACPI op and operand2 is an integer. Update name of function to reflect this and fix code to write integer instead of emitting byte for operand2. TEST=Verified by disassembling SSDT on reef that ACPI code generated for If with operand2 greater than 1 is correct. If ((Local1 == 0x02)) { Return (0x01) } Else { Return (Buffer (One) { 0x00 /* . */ }) } Change-Id: If643c078b06d4e2e5a084b51c458dd612d565acc Reported-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16Revert "ec/lenovo/h8: don't load configuration when booting from s3"Nico Huber
This reverts commit 83df672d2ce481686c5c4e04625bc1b97d7a4a8b. It's based on the assumption that the H8 keeps its configuration during a suspend/resume cycle. User reports indicate that this might not be true. Caching the settings in a cbtable entry might be a better approach. Change-Id: Ic4ba862ee7068ffe214c2aeaadecb4390a0e0529 Reviewed-on: https://review.coreboot.org/17411 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-11-15intel/apollolake: Ensure SPI operations do not cross 256-byte boundaryFurquan Shaikh
BIOS needs to ensure that SPI write does not cross 256-byte boundary. Else, if the write is across 256-byte boundary, then it corrupts the block by wrapping write to start of current block. Thus, ensure nuclear_spi_{read,write} operate within a single 256-byte block only at a time. BUG=chrome-os-partner:59813 BRANCH=None TEST=Verified that elog writes do not corrupt the event log when write is across 256-byte blocks. Change-Id: I854ca2979d65b9f1232f93182cb84d4dee4f4139 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-15northbridge/via/vx800: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/vx800. Change-Id: I14a2b4d847f8aeb327d90f385dea998779fae24f Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17316 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/via/cx700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/cx700. Change-Id: I6e25f898ab55ee959f1b3b8aba9616c3ba18986d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17315 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/intel/i855: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i855. Change-Id: Iae66d1ef838095a560868d9c9ff81f4208f814f1 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17314 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/amd/agesa/family10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/agesa/family10. Change-Id: I5723e217fc739ab576cbe3a1ee6d92023190267c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17313 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/vt8454c: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/vt8454c. Change-Id: I94e22e1d814733c4049e78e5b3c23b9bb429f6fa Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17312 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-m700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-m700. Change-Id: I7a16a9f396d50279cf2bd13de72bd78e8f53f7d8 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17311 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-cn: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-cn. Change-Id: I1b05abcedc427e4876e1fdab85298015308a3d17 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17310 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/tyan/s8226: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/tyan/s8226. Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17309 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15google/link/i915.c: Fix build error when native gfx init enabledIru Cai
- Move members of struct edid to struct edid_mode - Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/17332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-15nb/gm45: Refactor IGD vram decodingArthur Heymans
This is more consistent with other Intel GMCH code. Change-Id: I7bfaa79b9031e2dcc5879a607cadacbdd22ebde7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17405 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-14google/chromeec: Add elog events for recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified eventlog on reef 0 | 2016-11-12 19:49:25 | Log area cleared | 4088 1 | 2016-11-12 19:49:25 | Kernel Event | Clean Shutdown 2 | 2016-11-12 19:49:25 | ACPI Enter | S5 3 | 2016-11-12 19:49:39 | System boot | 365 4 | 2016-11-12 19:49:39 | EC Event | Power Button 5 | 2016-11-12 19:49:45 | Chrome OS Recovery Mode | Recovery Button Pressed 6 | 2016-11-12 19:49:45 | Chrome OS Developer Mode 7 | 2016-11-12 19:49:45 | EC Event | Keyboard Recovery 8 | 2016-11-12 19:49:45 | Memory Cache Update | Recovery | Success 9 | 2016-11-12 19:50:46 | System boot | 366 10 | 2016-11-12 19:50:46 | EC Event | Power Button 11 | 2016-11-12 19:50:52 | Chrome OS Recovery Mode | Recovery Button Pressed 12 | 2016-11-12 19:50:52 | Chrome OS Developer Mode 13 | 2016-11-12 19:50:52 | EC Event | Keyboard Recovery Forced Hardware Reinit 14 | 2016-11-12 19:50:52 | Memory Cache Update | Recovery | Success 15 | 2016-11-12 19:51:24 | Power Button 16 | 2016-11-12 19:51:24 | ACPI Enter | S5 17 | 2016-11-12 19:51:27 | System boot | 367 18 | 2016-11-12 19:51:27 | EC Event | Power Button 19 | 2016-11-12 19:51:32 | Wake Source | Power Button | 0 20 | 2016-11-12 19:51:32 | ACPI Wake | S5 21 | 2016-11-12 19:51:32 | Chrome OS Developer Mode 22 | 2016-11-12 19:51:32 | Memory Cache Update | Normal | Success Change-Id: I45dda210cf9d4e5a75404792fcee15b2010787a7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17394 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14vboot: Add new function for logging recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: I87cd675ea45a8b05a178cf64119bf5f9d8d218ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17408 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14elog: Update event log IDs for EC eventsFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: Idf2d377bf4709ea25616adfbde55f39798c0cd39 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17393 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14commonlib: Add new cbmem id for EC_HOSTEVENTFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully. Change-Id: Ife167bff484ef552bd6cd2e61fdc8291ad6a8acf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17392 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14lib/tpm2: do not create all NVRAM spaces with the same set of attributesVadim Bendebury
The TPM spaces created by the RO need to have different attributes depending on the space's use. The firmware rollback counter and MRC hash spaces are created by the RO code and need to be protected at the highest level: it should be impossible to delete or modify the space once the RO exits, and it is how it is done before this patch. The rest of the spaces should be possible to modify or recreate even after the RO exits. Let's use different set of NVRAM space attributes to achieve that, and set the 'pcr0 unchanged' policy only for the firmware counter and MRC cache spaces. The definitions of the attributes can be found in "Trusted Platform Module Library Part 2: Structures", Revision 01.16, section "13.2 TPMA_NV (NV Index Attributes)." CQ-DEPEND=CL:410127 BRANCH=none BUG=chrome-os-partner:59651 TEST=verified that the reef system boots fine in both normal and recovery modes; using tpmc confirmed that firmware, kernel and MRC cache NVRAM spaces are readable in both and writeable only in recovery mode. Change-Id: I1a1d2459f56ec929c9a92b39175888b8d1bcda55 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17388 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Pronin <apronin@chromium.org>
2016-11-14soc/intel/apollolake: Increase HEAP_SIZESathyanarayana Nujella
Adding both 2-ch & 4-ch DMIC blob causes the below error: memalign(boundary=8, size=3048): failed: Tried to round up free_mem_ptr 7abc48b0 to 7abc5498 but free_mem_end_ptr is 7abc4d70 Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr) Increased heap size fixes the above issue. BUG=chrome-os-partner:56918 BRANCH=none TEST=Compiles successfully for reef Change-Id: Ic910f169f7ef4bb746cb273e276428713a884227 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17157 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/intel/apollolake: Add support for DMIC 4ch & 1chSathyanarayana Nujella
Add NHLT support for DMIC Quad & Mono channel capture BUG=chrome-os-partner:56918 BRANCH=none Change-Id: If630ed53bb2cf00ccc441eb062b2e8c650d3cf01 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17156 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/nvidia/tegra210: Remove CONSOLE_SERIAL_TEGRA210_UART_CHOICESMartin Roth
The Kconfig symbol CONSOLE_SERIAL_TEGRA210_UART_CHOICES was attached to a choice, and isn't used anywhere. Remove it as unnecessary. Change-Id: I4efd2e43ac34b266db0d40d1bc8c123bd377b3a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-14intel/apollolake: Enable turboShaunak Saha
This patch adds punit initialization code after FspMemoryInit so that turbo can be initialized after that. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/17203 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/rockchip: split edp_enable() functionLin Huang
To avoid garbage display in firmware on warm reset, we need to enable eDP display in depthcharge instead when the framebuffer is cleared. Therefore limit edp_enable() in coreboot to just configure eDP, and leave enabling the display to depthcharge. CQ-DEPEND=CL:402071 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, and display work Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402095 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17207 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-14google/chell : update DPTF policy settingsSumeet Pawnikar
Fine tuned DPTF policy values for chell device as below, 1. Increase Passive temperature value to 52 degree Celsius for TSR2. 2. Remove charger effect for TSR2. 3. Increase Minimum PowerLimit1 to 3W. 4. Reduce Maximum PowerLimit1 to 6W. BUG=chrome-os-partner:54718 BRANCH=None. TEST=Built for chell device. Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14skylake: Update the thermal time window for throttling actionSumeet Pawnikar
This patch reduces the thermal time window to 100 milliseconds for fast throttling action at prochot. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the thermal time window value. Change-Id: If79d213cb8e19277ffdb882267d2f8672df93446 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17384 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14drivers/pc80/tpm: Select TPM device name based on Kconfig optionSubrata Banik
Device ID remains same for SLB9670 Infineon TPM 1.1 and TPM 2.0 chip. Hence select based on TPM2 Kconfig option. BUG=none BRANCH=none TEST=Build and boot SKL RVP with SPI TPM 2.0 module Change-Id: I57e63f2f2899d25ed6b797930fd8bf1d1cdc1b1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17374 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14intel/kblrvp: Enable TPMNaresh G Solanki
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support. Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb. Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-14riscv: add a variable to control trap managementRonald G. Minnich
This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-13Documentation: Add Kconfig documentMartin Roth
Change-Id: I99ca65343d52e99611644c0c65f4b7feb5c58436 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16947 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2016-11-13riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich
The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. Change the payload function to pass this string in a0. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17254 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12MAINTAINERS: Add lowrisc files to RISC-VJonathan Neuschäfer
Change-Id: I8e9ff5821e15cd9a5966927a8cd8bd95f7021d58 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17402 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12riscv: bring in the configstring parsing functions from UCBRonald G. Minnich
I've tested this with commits to come later. This is from the lowrisc bbl distribution, 87588c4, with fixes so it builds. Change-Id: I87893638872259c94d6972e1971578b633155e7e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17255 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-12drivers/intel/fsp2_0: track end of firmware notificationsAaron Durbin
The end of firmware notification is currently not being tracked so it's hard to get good data on how long it takes. Update the code to provide timestamp data as well as post codes. BUG=chrome-os-partner:56656 Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17373 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-12soc/intel/apollolake: cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. BUG=chrome-os-partner:56656,chrome-os-partner:59682 Change-Id: Iba87a51a05559d81b8e00fa4f6824dacf7a661f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17372 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12cpu/x86/mtrr: allow temporary MTRR range during corebootAaron Durbin
Certain platforms have a poorly performing SPI prefetcher so even if accessing MMIO BIOS once the fetch time can be impacted. Payload loading is one example where it can be impacted. Therefore, add the ability for a platform to reconfigure the currently running CPU's variable MTRR settings for the duration of coreboot's execution. The function mtrr_use_temp_range() is added which uses the previous MTRR solution as a basis along with a new range and type to use. A new solution is calculated with the updated settings and the original solution is put back prior to exiting coreboot into the OS or payload. Using this patch on apollolake reduced depthcharge payload loading by 75 ms. BUG=chrome-os-partner:56656,chrome-os-partner:59682 Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17371 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12soc/intel/common/lpss_i2c: configure buses by rise/fall timesAaron Durbin
The default register count calculations are leading to higher frequencies than expected. Provide an alternative method for calculating the register counts by utilizing the rise and fall times of the bus. If the rise time is supplied the rise/fall time values are used, but the register overrides take precedence over the rise/fall time calculation. This allows platforms to choose whichever method works the best. BUG=chrome-os-partner:58889 Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11lib/tlcl: Ensure tlcl library is initialized only onceFurquan Shaikh
Since tlcl library is used other than just vboot driver, ensure that the library is initialized only once per stage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified in recovery mode on reef, tlcl library is initialized only once in romstage. Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17364 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11samsung/stumpy: fix power LED operationMatt DeVillier
commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API] broke power LED operation when it incorrectly transferred values from the old function (it8772f_gpio_setup) to the new one ( it8772f_gpio_led). Restore the correct values so power LED illuminates when powered on. Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17266 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-11mainboard/google/snappy: Configure PERST pinWisley Chen
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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