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2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-28Add TCPA table.Vladimir Serbinenko
This allows SeaBIOS to fill it as necessary. This is needed to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-28to-wiki: Correct retreval of nice vendor nameVladimir Serbinenko
Change-Id: Ia1590e0bac5eefd4256bbbf5e8312a3dab7b5e6b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-28Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10322 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-27Deactivate TPMVladimir Serbinenko
Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27x201: Add TPM declaration.Vladimir Serbinenko
This allows to deactivate TPM on X201. Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10278 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27x230: Add TPM declaration.Vladimir Serbinenko
This allows to deactivate TPM on X230. Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10273 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27sandybridge native: Add call to TPM code.Vladimir Serbinenko
This allows to deactivate TPM on boards using native sandy/ivy init. Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10272 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-27AGESA binaryPI: Drop XIP_ROM_BASEKyösti Mälkki
Did we not get rid of this in 2011? Change-Id: I82cd7f0989e5d38e4a3b0067e471f7acdfd47543 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Copy gizmosphere/gizmo2 as bap/ode_e20XXKyösti Mälkki
Change-Id: I54a4719c571e18eb38a47e50ea69a4a85195d4dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10320 Tested-by: build bot (Jenkins)
2015-05-27AGESA: Reduce SPI use by 24kB for S3 supportKyösti Mälkki
There is no need to backup VolatileStorage in SPI flash at all. At the time we need it, we have CBMEM available. Change-Id: If0ca57b314140a833d6d59fe9e236e07816f05a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-27AGESA: Separate HeapManager declarations from BiosCallOutsKyösti Mälkki
Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10317 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-27AGESA: Split S3 backup in CBMEMKyösti Mälkki
Use separate CBMEM allocations for stack and heap on S3 resume path. The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE used on non-resume paths. Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-27arm64: Add weak implementation of soc_get_bl31_plat_paramsFurquan Shaikh
This function is required to be implemented by SoC only if some platform specific parameters are to be passed in from the early bootloader to bl31 component. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully. Change-Id: I6e76a0b6735267971e12aa72a987e8d83f5ad102 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ab8bc12ffc2ee5bf69cef68bae852dcbf7ccb98 Original-Change-Id: If55aaee8d18a8045a5d842145c0e2c97a37a8bca Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272377 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27arm64: Remove PLAT= variable initialization based on Kconfig variableFurquan Shaikh
Each SoC should have a BL31_MAKEARGS += ... defining all the make arguments required for bl31 component compilation. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully and boots into bl31. Change-Id: I20383ab61d012f7294d969f196044a5f1c07dfc1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 72bd297994248a9d96acc6f21d06bb6ff0d5292c Original-Change-Id: I1ddd5c38e9214021d857d9d586310e23fa4114e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272430 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10309 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27arm64: Pass in CROSS_COMPILE_arm64 for ARM TF compilationFurquan Shaikh
BUG=chrome-os-partner:40414 BRANCH=None TEST=ATF compilation successful Change-Id: Ib4eeced911181f756bd47c19eeb2d196ab5a0a2f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3061a219c24294a9fec4f26fc60b02f67bb55d66 Original-Change-Id: I39849d4048d7333eeab9bd698b4fd496181081a2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272374 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27xcompile: Add CROSS_COMPILE_* variableFurquan Shaikh
Add CROSS_COMPILE_* variable that can be passed to third-party component compilations. BUG=chrome-os-partner:40414 BRANCH=None TEST=CROSS_COMPILE_* variable is passed in correctly. Change-Id: I053325524601adf76ea35f7e74811fbc1c31781e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c07bd66e25900d064d6c69bddada67112ba5f183 Original-Change-Id: I3e4a5262acd84830205f64ba9a935974dd36ebbd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272372 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10306 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27veyron_brain: Remove unused USB GPIOsDavid Hendricks
Brain doesn't have HOST1_PWR_EN (GPIO0_B3) and 5V_DRV (GPIO7_C5). The only USB power enable pin connected to the AP is USB2_PWR_EN (GPIO0_B4) which controls power for both the physical type-A ports. BUG=none BRANCH=none TEST=built and booted on Brain, both USB host mode ports work Change-Id: Iea371926c7dcd111aa2e671a15fe97a3519bfc04 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db71095a5116666cd27aedb09b4f02557362346 Original-Change-Id: Ibbb4b9b424156eb3db1ccfdd948050c1c067ad3c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271309 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@google.com>
2015-05-26vboot: move to region_devicesAaron Durbin
Now that vboot is using offsets for everything remove the pass through vboot_get_region() and use region_devices as first class citizens. Change-Id: I1a86f3725e5bce38e6ca31e9641b1a8f4ac50e96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26vboot: use only offsets for tracking firmware componentsAaron Durbin
Because of the fmap API returning pointers to represent regions within the boot device a vboot_region structure was used to track the case where offsets could be pointers on x86 but not on !x86. Normalize this tracking to use offsets only as it provides consistency in the code. Change-Id: I63c08b31ace3bd0e66ebc17e308f87eb5f857c86 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26cbfs: remove unused CBFS_HEADER_ROM_OFFSET optionAaron Durbin
The CBFS_HEADER_ROM_OFFSET went away. Remove remaining defintions that are not used. Change-Id: Ibedce988143f0b7167cea1b27de5b33698b5d82b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26coreboot: introduce boot_deviceAaron Durbin
The boot_device is a region_device that represents the device from which coreboot retrieves and boots its stages. The existing cbfs implementations use the boot_device as the intermediary for accessing the CBFS region. Also, there's currently only support for a read-only view of the boot_device. i.e. one cannot write to the boot_device using this view. However, a writable boot_device could be added in the future. Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10216 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26pistashio: bump up romstage sizeAaron Durbin
Making large changes in pieces is leading to a little bloat. Bump up the romstage size temporarily so that jenkins will be happy. Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26Make acpi_fill_hest into parameterVladimir Serbinenko
This avoids the need to supply weak function and avoids associated risks of forgetting to link in relevant files. Change-Id: Ie96475babb4aa4ea8db49023af5b31bfa63b21dc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7373 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7367 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26acpigen: Remove acpigen_patch_lenVladimir Serbinenko
Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7365 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26pcengines/apu1: Enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: apu1c models do not support this. That we expose S3 in ACPI table while it is not available, is a wider issue to solve. Change-Id: I9b07550d0523593f51c1882a40cccd783115057b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10315 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26AGESA: Halt on S3 resume failureKyösti Mälkki
Change-Id: Ib6ac8ab3aca991fa623fedcd87a20470248d58e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10298 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Split S3 support fileKyösti Mälkki
Separate it to low-memory backup in romstage and MTRR recovery in ramstage. How much of the MTRR part we really need will be resolved later. Change-Id: Ic64b3f74cf6ef0954eda6e84754745de81c465b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Refactor OEM S3 storageKyösti Mälkki
Use function prototypes that match more closely with the structure of other OEM hooks in agesawrappers. Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Move S3 related SPI writes againKyösti Mälkki
This is more agesawrapper-related code than CPU. Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26cbmem: remove cbmem_set_top()Aaron Durbin
Now that the users of cbmem_set_top() always provide a consistent cbmem_top() value there's no need to have cbmem_set_top() around. Therefore, delete it. Change-Id: I0c96e2b8b829eddbeb1fdf755ed59c51ea689d1b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10314 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26CBMEM console: Fix buffer without EARLY_CBMEM_INITKyösti Mälkki
On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage, even when romstage did not create it. So buffer did not get cleared on S3 resume path. Also do not allocate for preram_cbmem_console in CAR when there are no means to back it up to ram. Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-26timestamp: Fix collection without EARLY_CBMEM_INITKyösti Mälkki
With LATE_CBMEM_INIT, do not search for the initial collection from CBMEM in ramstage. On S3 resume this would find the non-empty collection from previous run of ramstage. Start with an empty table instead. Remove a spurious error message as the stamps get stashed and will be copied to CBMEM later. Change-Id: Ib94049531c0ac23af25407bd2ca7644ee0163d69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26CBMEM: Fix S3 resume path without EARLY_CBMEM_INITKyösti Mälkki
Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10299 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-26x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INITAaron Durbin
For x86 systems employing CONFIG_LATE_CBMEM_INIT, set_top_of_ram() is called in ramstage to note the upper address of the 32-bit address space. This in turn is consumed by cbmem. However, in this scenario cbmem_top() cannot always be relied upon because get_top_of_ram() doesn't return the same value provided to set_top_of_ram(). To fix the inconsistency in ramstage save the value passed in to set_top_of_ram() and defer to it as the return value for cbmem_top(). Change-Id: Ida796fb836c59b9776019e7f8b3f2cd71156f0e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10313 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-05-26consoles: remove unused infrastructureAaron Durbin
The __console attribute as well as linker binding was dropped at some point. Kill of the dead code and infrastructure. Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26AGESA f16kb: Fix PCI device notationFabian Kunkel
Old file defines wrong PCI devices (1.2 2.2 3.2 4.2 5.2). Wrong defines cause PCI devices not to be found in the pirq_data table. Example error output: PCI IRQ: Found device 0:02.01 using PIN A PCI Devfn (0x11) not found in pirq_data table PCI IRQ: Found device 0:02.02 using PIN B Found this device in pirq_data table entry 3 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x02 (INTC# ) INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:02.03 using PIN C PCI Devfn (0x13) not found in pirq_data table PCI IRQ: Found device 0:02.04 using PIN D PCI Devfn (0x14) not found in pirq_data table PCI IRQ: Found device 0:02.05 using PIN A PCI Devfn (0x15) not found in pirq_data table Patch fixes, that pirq_data entries for pci devices 2.1 - 2.5 get found. Change-Id: I4503433427f4ec90d022b65084c52077ba4f3511 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10289 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26ACPI: slic supportVladimir Serbinenko
Export SLIC table from file in CBFS. Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7202 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26gm45: Link cstates.c rather than including it.Vladimir Serbinenko
The comment about necessity of include isn't true anymore as get_cst_entries is not weak anymore so if it's not found, the linking would fail. Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7375 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26bd82x6x: Merge common platform ASL code.Vladimir Serbinenko
This code in reality just describes the southbridge features, don't put a copy in every mainboard. Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10231 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2015-05-26cbfstool: update fmd_scanner.c_shippedPatrick Georgi
We updated the source files, but not the precompiled results. Change-Id: I49634409d01c8d7cf841944e01d36571ae66c0ac Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10296 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26build system: only query the compiler runtime's location oncePatrick Georgi
No need to execute the compiler to figure this out once for each source file (or so). Change-Id: I56bf084f1217b96748296931617e9233f21183d5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10294 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-26cbfstool: Make update-fit action work on new-style imagesSol Boucher
Because new images place the bootblock in a separate region from the primary CBFS, performing an update-fit operation requires reading an additional section and choosing a different destination for the write based on the image type. Since other actions are not affected by these requirements, the logic for the optional read and all writing is implemented in the cbfs_update_fit() function itself, rather than relying on the main() function for writing as the other actions do. Change-Id: I2024c59715120ecc3b9b158e007ebce75acff023 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-25gitignore: Have multiple crossgcc versionsKyösti Mälkki
Make it so that git does not remove old copies or the symlink. Change-Id: I27be60c897d2f86cdf274480c83cbbfe38fcdf94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10292 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-25inteltool: dump gfx registers.Vladimir Serbinenko
Useful for autoport and other gfx-related developpement. Change-Id: I1fc0952bc30ab15cd39a4f0c00649714dcf318f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10276 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 17:45:13 +0000