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2019-05-29Documentation: Warn about ME cleaner on Sandy BridgePatrick Rudolph
Document known issues with 'disabled' ME. Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29mb/google/sarien: Send post code to the ECEric Lai
Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29arch/x86: Do not add properties to null DP packagesJacob Garber
It doesn't make sense to add a property to a non-existent Device Property package. However, some of these functions will proceed anyway and allocate a new Device Property package, add the property to that, and then immediately leak the new package. This changes all the acpi_dp_add_* functions to ignore a null package. Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 135745{6,7}, 138029{2-6} Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variantsIvy Jian
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.108.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29nb/intel/nehalem: Call smm_region_start() functionArthur Heymans
This also removes the unnecessary mask. TEST: X201 Boots again. Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-29drivers/intel/fsp2_0: Fix typo mistakeSubrata Banik
Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-05-28util/xcompile/xcompile: apply -march to clang as well as gccAlan Green
For x64 and x86_32 configurations, apply the -march flag to both GCC and Clang flags. This solves the problem of Clang-compiled coreboot failing due to Clang emitting SSE instructions for code that is executed while SSE is not enabled. This patch takes functionality targeted for GCC configurations and moves it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order that it applies to both GCC and Clang. This is an alternate patch to CB:32887. Signed-off-by: Alan Green <avg@google.com> Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-28soc/intel/cannonlake: Dump ME status info before notify EndOfFirmwareBora Guvendik
Dumping ME status displays wrong information if we disable Heci1 because it is called after fsp notifies EndOfFirmware and disables Heci1. This patch moves the ME status dump before fsp notify EndOfFirmware. TEST=Boot to OS, check ME dump information Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-28mb/google/sarien: Modify SSD power sequenceEric Lai
Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28mb/google/sarien: Fix SSD power leakage in S5Eric Lai
Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28src/arch/x86: Add automatic type41 entry creationChristian Walter
SMBIOS Type41 Entries will be automatically created. Type 41 entries define attributes of the onboard devices. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28src/cpu/x86/lapic/lapic.c: Add missing newlineChristian Walter
Added missing new line to Info Output. Change-Id: Ic4cd63f231de918fad7cd34724651bf8eb1c8e62 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-28src/include/device/pci_ids.h: Add Kabylake C236 DeviceChristian Walter
Change-Id: Ib11981543575311a32896df385d44cf30aa9387f Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28mb/google/sarien: Modify arcada touchscreen reset delayCasper Chang
Modify reset delay to 20ms of touchscreen to address i2c hid driver rebind failed issue after auto update of touchscreen firmware BUG=b:132211627 TEST=Touchscreen works after auto update and no re-bind driver failed issue Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-27sb/intel/common/smi.c: Remove unused functionsArthur Heymans
Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-27cpu/intel/model_2065x: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27cpu/intel/model_2065x: Use parallel MP initArthur Heymans
TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core). Boots ~28ms faster. Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27sb/intel/ibexpeak: Use common Intel SMM codeArthur Heymans
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0Arthur Heymans
drivers/intel/fsp1_0/Kconfig is a better location than cpu/x86/Kconfig. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-27drivers/intel/fsp1.1: Remove unused functionArthur Heymans
This function is unused since POSTCAR_STAGE is used. (be291e8 soc/intel/fsp1.1: Implement postcar stage) Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-27drivers/intel/fsp1.1: Remove stale comment on bootflowArthur Heymans
This list is incorrect and not up to date. The FSP1.1 romstage bootflow is unnecessarily clumsy and instead of trying to update this comment effort is better spend making the bootflow more streamlined. Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-27libpayload: Reset PS/2 keyboardPaul Menzel
Loading a libpayload based payload like coreinfo or FILO from SeaBIOS or GRUB pressing keys does not give the expected results. For example, pressing F1 gives the character 24 translated to scan code 6a. ESC for example 43 (111) in coreinfo loaded from SeaBIOS on QEMU Q35. The problem is not reproducible using the payload directly, that means without SeaBIOS or GRUB. The problem seems to be, that those have already initialized the PS/2 controller and AT keyboard. Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to be reset. That seems to fix the issue, when the keyboard was initialized before. TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary payload. Run qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio press 3 to select the coreinfo payload, and verify that the keys F1 and F2 are working. Same with coreinfo loaded from GRUB on the ASRock E350M1. Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-25nb/intel/pineview: Use MTRR as a proxy for proper resetArthur Heymans
On reset this platform can sometimes hang. This also fixes pineview mainboards not building due to the symbol 'check_mtrr' lacking. Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-25superio/fintek/f71863fg: Remove variable set but not usedElyes HAOUAS
Change-Id: I993055d237b2bd607822485d34d5508c74a7744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-25nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-25Documentation: Add HP EliteBook 8760wIru Cai
Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25mb/lenovo: Unify thermal threshold handlingPeter Lemenkov
Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25AGESA binaryPI: Add AGESA entry timestampsKyösti Mälkki
The call to timestamp_rescale_table() had to be moved before TS_AGESA_INIT_{POST/RESUME}_DONE to have that timestamp appear without rescaling. Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-25AGESA binaryPI: Redo entrypoints namelistKyösti Mälkki
Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-25AGESA: Move debug helper to eventlog fileKyösti Mälkki
Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31513 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25AGESA f12 f14 vendorcode: Clean up extra CFLAGSKyösti Mälkki
Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-25AGESA: Move heap_status_name() implementationKyösti Mälkki
Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-24ec/google/wilco: Fix radio control commandDuncan Laurie
This command is working as written, but it is not actually correct as to what the format of the command should be. Fix this and add define the other radios. There is no change in the command send to the EC. Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-05-24nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24nb/northbridge/intel/x4x/acpi.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I715adbe3d90d0f5195b54c274fb7843945d3e6be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-24nb/amd/amdmct/mct/mctpro_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: Ic2f2788142329e2e4d04b531805a32d4dcaa293c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32949 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-24nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24nb/amd/pi/00660F01: Remove variable set but not usedElyes HAOUAS
Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24superio: Add ASpeed AST2400Frans Hendriks
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-23soc/intel/skylake: Add PCI Id for Kabylake DTChristian Walter
Change-Id: I496b3a91f765d4fa137c32c9ee1e244803fc25d8 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32850 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23Renumber cbtable tag MMC_INFOPatrick Georgi
We got another tag in the meantime, so resolve the conflict. Change-Id: I64cb5e02a9bed3d8746b75e451c13a1598341ba1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32954 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23coreboot_tables: pass the early_mmc_wake_hw status to payloadBora Guvendik
Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23intel/common/block/scs: Add ability to send early CMD0, CMD1Bora Guvendik
In order to improve boot time with emmc, add ability to send CMD0 and CMD1 early in romstage. This way, by the time system boots to payload, we are ready to continue with emmc setup and we don't need to send CMD0 in payload again, and wait for card to reset and be ready. BUG=b:78106689 TESTS = Boot to OS Force early_mmc_wake_hw() to return error, recover in payload Force an error in payload, make sure system can recover/boot Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-23mb/google/hatch/variants: Fix DPTF sensor IDsEvan Green
There are indeed two temperature sensors hooked up to the EC, but they are indexed as 0 and 1, not 1 and 2. BUG=b:132999028 TEST=Boot hatch with hardened EC, observe no more index overflows Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-23util/romcc: Add extra null pointer checkJacob Garber
It is possible that 'lnode->val' is set to 0 on a previous iteration of the loop, so check that it is non-null here before dereferencing it. Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1129149 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Fix memory leakJacob Garber
The 'new_type' function already allocates memory, so it is only necessary to clone the existing type if this function is not called. Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity Scan CID 1129106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Add null check for filenameJacob Garber
It is possible that 'filename' is still null in this if statement, so we add an extra check to prevent a null dereference in strcmp. Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1395330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Add extra NULL checks for memberJacob Garber
In each of these cases it is possible that 'member' is NULL at the beginning, which will skip the earlier while loops entirely and cause a NULL dereference later on. Add extra error checks to prevent this. Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23AGESA binaryPI: Sync STRUCT_NAME definitionsKyösti Mälkki
While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of preprocessor directives. Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31510 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23util/autoport: Mention i2c-i801 module in readme.mdEvgeny Zinoviev
SMBus adapter will not appear if i2c-i801 module is not loaded. Added it to the readme. Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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