summaryrefslogtreecommitdiff
path: root/Documentation/mainboard
AgeCommit message (Collapse)Author
2019-11-17mainboard: Add Clevo W650SZIru Cai
This port is based on the code generated with autoport with Haswell support (30890). It can boot Arch Linux from mSATA or USB with SeaBIOS payload. The EHCI debug port is at the right hand side of the laptop, but the debug message stops to display after mrc.bin initializes USB. Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2019-11-15Documentation/mb/facebook/fbg1701.md: Update microcode blobFrans Hendriks
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15Documentation/mb/portwell/pq7-m107.md: Update microcode blobWim Vervoorn
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01Documentation: Fix typoPatrick Rudolph
The document isn't included in any toc-tree due to a typo. Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36540 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/portwell/m107: Add Kingston memory supportWim Vervoorn
Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft
- This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-23mb/supermicro/x11-lga1151-series: add x11ssm-f boardMichael Niewöhner
This adds another x11 series board, the X11SSM-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and Ethernet interfaces. Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner
2019-10-20mb/lenovo/x200: Add ThinkPad X301 as a variantBill XIE
It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16Documentation/mainboard/facebook: Add rev 1.3Wim Vervoorn
Add rev 1.3 of the fbg1701 board. This adds Kingston memory. BUG=none TEST=none Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-15soc/intel/common/block/sgx: Fix crash in MP initPatrick Rudolph
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written when already locked by the sibling thread. In addition it loads microcode updates on all threads. To prevent such race conditions only call the code on one thread, such that the MSRs are only written once per core and the microcode is only loaded once for each core. Also add comments that describe the scope of the MSR that is being written to and mention the Intel documents used for reference. Fixes crash in SGX MP init. Tested on Supermicro X11SSH-TF. Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15mainboard/lenovo/t410: Add new portNicolas Reinecke
The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-07src: Capitalize Super I/OElyes HAOUAS
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-07Documentation/mb: Link AMD mainboards directly in the big listPatrick Georgi
Fixes an issue with amd/index.md not being part of a toctree Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07Documentation/mb/amd/padmelon: Fix relative linkPatrick Georgi
Change-Id: I132aed69107153785c5e824108677e60243483ce Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-04mb/supermicro/x11-lga1151-series: rework documentationMichael Niewöhner
This splits the x11-lga1151-series' documentation into a generic and a board specific section as a preparation for CB:35427. Additionally this adds some more information on the x11ssh board. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c Reviewed-on: https://review.coreboot.org/c/coreboot/+/35547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-01Documentation/mainboard/amd: Add padmelon documentation and imagesRichard Spiegel
Create documentation on padmelon, including how to program the SPI. Also include an index.md pointing to the documentation, as currently there's no maiboard documentation folder for AMD. BUG=none. TEST=none. Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26mb/supermicro: restructure x11ssh-tf to represent a x11 board seriesMichael Niewöhner
Most of the X11 boards with socket LGA1151 are basically the same boards with just some minor differences like different NICs (1 GbE, 10 GbE), number of NICs / PCIe ports etc. There are about 20 boards that can be added, if there is a community for testing. To be able to add more x11 boards easily like x11ssm (see CB:35427) this restructures the x11ssh tree to represent a "X11 LGA1151 series". There were multiple suggestions for the structure like grouping by series (x10, x11, x...), grouping by chipset or by cpu family. It turned out that there are some "X11 series" boards that are completely different. Grouping by chipset or cpu family suffers from the same problem. This is why finally we agreed on grouping by series and socket ("X11 LGA1151 series"). The structure uses the common baseboard scheme, while there is no "real" baseboard we know of. By checking images, comparing logs etc. we came to the conclusion that Supermicro does have some base layout which is only modified a bit for the different boards. X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we expect the other boards to have mostly the same device tree, there is a common devicetree that gets overridden by each variant's overridetree. Besides that some very minor modifications happened (formatting, fixing comments, ...) but not much. Documentation is reworked in CB:35547 Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22Documentation: Capitalize Super I/OPaul Menzel
Change-Id: I6bfe11abc1b3763f3d6c390bbccd9191b417945d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-20Documentation: X11SSH-TF update known issuesPatrick Rudolph
Change-Id: I5811fb829b45381ac19b2c3f2411c91f85b61d08 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-20Documentation/mainboard: Fix indexNico Huber
Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16Documentation: rename "Rookie guide" to "tutorial"Patrick Georgi
We generally try to stay away from ascribing attributes to (future) devs. "Rookie guide" refers to the reader, while "tutorial" refers to the material. In the same spirit, move from "lessons" to "parts". It's not school :-) Change-Id: I11a69a2a05ba9a0bc48f8bf62463d9585da043ec Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-01mb/supermicro/x11ssh: Add Supermicro X11SSH-TFChristian Walter
Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBIOS payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init Not working: * TianoCore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Singer <felix.singer@9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-26mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MBAsami Doi
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M) that’s possible with QEMU on AArch64 virt because it tries to search the DRAM_SIZE_MB range to find the true memory size. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-08mainboard/emulation/qemu-aarch64: Add new board for ARMv8Asami Doi
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-06Documentation: Advertise support for OpenSBIPatrick Rudolph
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-07-17mainboard/portwell/m107: Do initial mainboard commitFrans Hendriks
Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-27mainboard: Add support for ASUS P8Z77-M PRO desktop mainboardVlado Cibic
Add support for ASUS P8Z77-M PRO desktop mainboard Working: - Tianocore and SeaBIOS boot - PS/2 keyboard and mouse - Audio - S3 Suspend, shutdown and reboot - USB2 / USB3 - Gigabit Ethernet - SATA3, SATA2 and eSATA - NVME - CPU Temp sensors - TPM - Native raminit and also MRC - PCIe GPU in all PCIe slots (16x/8x/4x) (linux) - Integrated graphics with both libgfxinit and Intel Video OpROM (all connectors VGA/DVI-D/HDMI) Signed-off-by: Vlado Cibic <vladocb@protonmail.com> Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/33328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-24Documentation: Add PC Engines apu2Piotr Kleinschmidt
Describe how to run coreboot on the PC Engines apu2 mainboard. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-24Documentation: Add PC Engines apu1Piotr Kleinschmidt
Describe how to run coreboot on the PC Engines apu1 mainboard. Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-17doc/mb/upsquared: Add documentationFelix Singer
This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-06mb/hp: Add Z220 SFF workstationPatrick Rudolph
* Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mainboard/facebook/fbg1701: Do initial mainboard commitFrans Hendriks
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-30mb/roda/rk9: Document flash headerNico Huber
Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-25Documentation: Add HP EliteBook 8760wIru Cai
Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23mb/asus/p8h61-m_pro: Add small fixesPatrick Rudolph
* Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-22mb/up/squared: Add mainboardFelix Singer
Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21Documentation: Add RotunduPatrick Rudolph
Add information about flash and programming header. Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-06Documentation: Add MSI MS-7707Bluemax
Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23hifive-unleashed: update documentation to match current statePhilipp Hug
Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-11Documentation: Make lenovo codenames human readablePatrick Rudolph
Use rst parser to convert the csv to markdown tables. Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-10Doc/mb/asrock/h110m: update info about PEGMaxim Polyakov
- Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported. Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06Doc/mb/asrock/h110m: Fix the linksMaxim Polyakov
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-19mainboard: Add ASRock H110M-DVSMaxim Polyakov
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard. Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio. TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation. Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload. Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-14Documentation: Add Asus F2A85-MBalazs Vinarz
Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-26mb/qemu-riscv: update to match current qemu versionPhilipp Hug
Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17mb/lenovo/x220: Add x1 as a variantBill XIE
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09Doc/mb/asrock/h81m-hds: Link to the Haswell documentationTristan Corrick
Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-09Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixedTristan Corrick
The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Also add a link to the known issues for Haswell, which has some information on PCIe. Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixedTristan Corrick
PCIe graphics for display output still doesn't work, but that is now listed in the Haswell-specific documentation. Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 07:56:49 +0000