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2021-05-21mb/hp: Add EliteBook 820 G2Iru Cai
It can now boot Arch Linux from SATA and USB. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2021-05-20Doc/releases: Mention that Asus H61 boards got squashedAngel Pons
Not physically squashed, the coreboot code got turned into a variant setup with override devicetrees to drop redundant boilerplate. Change-Id: I7ae5530d2603d6d108ef3829004de7e1cad130f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-19tests: improve code coverage supportPaul Fagerburg
Fix the exclusion path for lcov; it should exclude the directory with source code, not object files. Use the COV environment variable to * control whether we build for coverage or not * select the output directory Add a separate target for generating the report, so we can get a report for all of the tests together or just a single test. Add documentation. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-05-17Documentation/gerrit: Describe core developer responsibilitiesPatrick Georgi
Change-Id: I8885e9fb401838229ead72b97394f3e2343aabed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-16Documentation/distributions: List System76Paul Menzel
Copy the text from the [Web site](https://coreboot.org/users.html). Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-14Documentation/distributions: Order vendor list lexicographicallyPaul Menzel
Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-05-14Documentation/distributions: Separate all vendors by exactly one blank linePaul Menzel
Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-14Documentation/distributions: Separate parenthesis by dashesPaul Menzel
Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-13payloads/Tianocore: Update default build target, simplify build optionsMatt DeVillier
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig option since it applied only to CorebootPayloadPkg. Clean up the Makefile now that we're only building from a single Tianocore package/target. Test: build/boot qemu Q35 target with both UefiPayload and Upstream options. Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12Doc/nb/intel/sandybridge: Fix up some typos and cosmeticsAngel Pons
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-12Documentation/releases: Add more details about release notesPatrick Georgi
There are some steps when updating the release notes that are easily missed (see: I missed them for 4.14), so document them. Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation/releases: Add 4.15 release notes templatePatrick Georgi
Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation/releases: Update checklistPatrick Georgi
Since we want commits to go through 24 hours of review, move the vboot list update a week earlier. Also point more directly at the right script to execute. Change-Id: I49e6dfe22894402d5a0526588f8a04595ac88862 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation: Update vboot support listPatrick Georgi
Created by util/vboot_list/vboot_list.sh Change-Id: I49536c26540c0fd1940a32f588fa49afb55b108a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-11docs: add recommendation for gpios regarding soft strapsMichael Niewöhner
Soft straps, that can be configured by the vendor in the Intel Flash Image Tool (FIT), can influence some pads' default state. It is possible to select either a native function or GPIO mode for some pads on non-server SoCs, while on server SoCs most pads can be controlled. Thus, add a recommendation to always configure all pads for a board to guarantee integrity between different board or vendor firmware revisions where the soft straps might have been changed. Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-11docs: correct and rewrite documentation regarding n/c / unused padsMichael Niewöhner
Intel PDGs starting from Skylake / Sunrise Point state that, different from the general recommendation in digital electronics, unconnected GPIOs defaulting to GPIO mode do explicitly not require termination. The reason for this is, that these GPIOs have the `GPIORXDIS` bit set, which effectively disconnects the pad from the internal logic by disabling the input buffer. This bit - besides `GPIOTXDIS` - can also be set explicitly by using the gpio macro `PAD_NC(pad, NONE)`. In some cases, a pull resistor may be required due to bad board design or when a vendor sets the RX/TX disable bits together with a pull resistor and schematics are not available to check if the pad is really unconnected or just unused. In this case the pull resistor should be kept. Pads defaulting to native functions usually don't need special handling. However, when pads requiring external pull-ups are missing these due to bad board design, they should be configured with `PAD_NC` to disconnect them internally. Rewrite the documentation to reflect these new findings. Also clarify the comment in soc/intel gpio code accordingly. Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10Documentation/releases: Fill in coreboot 4.14 release notesPatrick Georgi
Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10doc/relnotes/4.14: add Intel Xeon-SP support status changeJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changesKyösti Mälkki
Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-09Documentation/gerrit: Document our Gerrit user roles and proceduresPatrick Georgi
Document the roles we have on review.coreboot.org, the expectations associated with them, and how to become part of any of these groups. Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52265 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne additionFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/i2c/generic: Set S0W to D3hot for wake deviceTony Huang
If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-03util/sconfig: Add support for discontiguous FW_CONFIG fieldsTim Wawrzynczak
Sooner or later, some board was going to need extra FW_CONFIG bits for a field that was already in production, so this patch adds support for adding extra (unused) bits to a field. The extra are appended via a syntax like: `field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...` and the suffixed bits are all treated as if they are contiguous when defining option values. BUG=b:185190978 TEST=Modified volteer fw_config to the following: field AUDIO 8 10 | 29 29 | 31 31 option NONE 0 option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 option RT1011_ALC5682I_I2S 6 option AUDIO_FOO 7 option AUDIO_BAR 8 option AUDIO_QUUX 9 option AUDIO_BLAH1 10 option AUDIO_BLAH2 15 option AUDIO_BLAH3 16 option AUDIO_BLAH4 31 end which yielded (in static_fw_config.h): FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700 Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747 Reviewed-by: Duncan Laurie <duncan@iceblink.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29docs/mb/supermicro/x11ssm-f: rework flashing sectionMichael Niewöhner
The board can be flashed without adding a diode by just leaving VCC unconnected. Rework the flashing section to describes that. Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/asus/p5q: Document working fan control and FireWire portStefan Ott
Fan control and FireWire work fine on my board. Signed-off-by: Stefan Ott <stefan@ott.net> Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26mb/system76/oryp6: Add System76 Oryx Pro 6Tim Crawford
https://tech-docs.system76.com/models/oryp6/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe - M.2 SATA - MicroSD card slot - All USB ports - Integrated graphics using Intel GOP driver - Webcam - Ethernet - Internal microphone - Combined headphone + mic 3.5mm jack - Combined microphone + S/PDIF 3.5mm jack - Booting to Ubuntu Linux 20.10 and Windows 10 - Flashing with flashrom Not working: - S3 suspend/resume: System hangs on wake from S3 - Discrete/Hybrid graphics: Requires a new driver - Internal speakers: Enabled in separate patch Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16[RFC] Address the leftover TODO in soc/intel/cannonlakeFurquan Shaikh
Change-Id: I4c989de4d2af3e810fb0e4803d0fa2396917d93e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50829 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15Documentation: List the leadership meeting as one of our forumsPatrick Georgi
Change-Id: I00822cc631c5451862bd94683ff45289ecc75679 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-04-15sc7280: Provide initial SoC supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15Documentation/mb/ocp: Update Delta Lake documentationJonathan Zhang
Update OCP Delta Lake documentation following OSF (Open System Firmware) solution reaching DVT exit parity. This alternative host firmware solution uses FSP/coreboot/Linuxboot stack. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06Docs/mb/lenovo/t420: List working, tested and non-working featuresPiotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl> Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-03docs/mb/supermicro: add SUM tool for flashing with disabled MEMichael Niewöhner
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/purism/librem_14: Move/fix touchpad interrupt GPIOMatt DeVillier
On production boards, the touchpad interrupt line was moved from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry, and update documentation to remove touchpad config issue. Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28documentation: Add documentation for Purism Librem 14Matt DeVillier
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26Documentation/coding_style: Issues not mentioned and cleanup patchesJulius Werner
This patch adds a bit of a "preamble" to the coding style to provide guideance on how it should be applied and how style questions that aren't mentioned should be handled. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22Documentation/coding_style: Add more details on include-orderingJulius Werner
This patch is trying to address some of the concerns raised in CB:50247 after the patch had landed. The preference for alphabetized headers was just supposed to discourage leaving headers completely unordered, and wasn't intended to disallow other intentional include orderings such as grouping local includes after system ones or specific ordering constraints that exist for technical reasons. This patch adds a few more sentences to try to clarify that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6825f4a57613fabb88a00ae46679b4774ef7110b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19doc/mb/lenovo/montevina: Update link within pageAngel Pons
Commit c4aa24fc121 (doc/mb/lenovo/montevina: Clarify use of bincfg) renamed a section, and the link referencing it by its old title no longer works. Update the link, and remove the `a completely new one` part from it as well, for consistency with the aforementioned commit. Change-Id: I22e8b3237dafb3397bc901804a57e905f806839d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-18Documentation/releases: Add note about CBFS stage format changePatrick Georgi
Change-Id: I2e4f1d1551141c6225e762631e52d71357112425 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-17Documentation: Describe the site-local hook in our config/build systemPatrick Georgi
Change-Id: Ia682b784540fa82e1f216f76d87d59a4f0b94486 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51546 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17Documentation: Add deprecation notice for SAR support in VPDFurquan Shaikh
This change updates the release notes for coreboot-4.14 to add deprecation notice for SAR support in VPD for Chrome OS platforms. BUG=b:173465272 Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-14doc/mb/lenovo/montevina: Fix constants for 16MiB flashNico Huber
The current values are actually for 32MiB and result in a brick if used with a 16MiB chip because of the invalid bios region. Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11Documentation/acpi: switch example from edge to level interruptsDmitry Torokhov
Configuring touch controllers to use edge-triggered interrupts is not recommended as it is very easy to lose an edge when kernel drivers disable the interrupt for one reason or another, and recovering from this condition requires workarounds in the kernel. Unfortunately the example setting up a touchpad used edge-triggered interrupts, and this set up has been propagating through the boards. Let's switch the example to use level interrupts instead. Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-07doc/mb/lenovo/montevina: Clarify use of bincfgNico Huber
`bincfg` is not creating anything new, it just converts from text to binary. Change-Id: I14e67ee8bc449d171a951f6edeaa9f9d0c04dbe1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51319 Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26mb/google/trogdor: Add new configs homestarxuxinxiong
New boards introduced to trogodor family. BUG=b:180668002 BRANCH=none TEST=make Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-24doc/mb/ocp: Update DeltaLake for VPD variables used in LinuxBootJohnny Lin
u-root commits: bmc_bootorder_override https://github.com/u-root/u-root/pull/1902 systemboot_log_level: https://github.com/u-root/u-root/pull/1922 Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-23Doc/releases/checklist.md: Clarify tag push commandAngel Pons
Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47813 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 20:41:03 +0000