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2018-04-17Use git HTTP URLs without `/p` in itPaul Menzel
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25545 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16Documentation/acpi/gpio.md: Fix formatting of tableJonathan Neuschäfer
The table in Documentation/acpi/gpio.md is currently detected as free-form text (at least by GitHub and recommonmark), instead of a table. Wrap it in a code formatting block to preserve the manual formatting. Change-Id: If460d7f1ba1a6198d949886f0f55fd6254bc2f7a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16Documentation/acpi/gpio.md: Fix markdown heading levelsJonathan Neuschäfer
Only the document title should be a top-level heading ('#'). Everything else should be a second- over lower-level heading ('##'). Also remove the '#' sign at the end of heading lines. "# Foo #" is mentioned as a valid syntax variant at [1], but it's quite uncommon. [1]: https://daringfireball.net/projects/markdown/syntax#header Change-Id: Ida16c3ecaa22e8439007673cb943d04952e19471 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-10Documentation: Fix a bunch of typosJonathan Neuschäfer
Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10Documentation: Rename submodules.txt to submodules.mdJonathan Neuschäfer
This will help static site generators that can turn Markdown into HTML but can't easily turn plain text into HTML. Change-Id: Iabdbbecd0badddbca2221c6164b254ca163555ad Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-10Documentation: Convert abi-data-consumption.txt to MarkdownJonathan Neuschäfer
This will help static site generators that can turn Markdown into HTML but can't easily turn plain text into HTML. Change-Id: Id186db140503f3c2759d579b18476fff021988c8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-09Documentation/Intel: Add NativeRaminit documentationPatrick Rudolph
Add documentation for Intel native raminit on Intel SandyBridge. Documented so far: * Register * Read training * Frequency selection * SMBIOS type 17 memory reporting * Various Kconfig options and features Change-Id: I3b977460ecb29c9a54e3fab82349982fca9918e7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-14Documentation/Intel/vboot: Remove double word *after*Werner Zeh
Change-Id: I5332c5760987d6ca6e92ac8aae7f3d43e09e8e4e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03Documentation: add thinkpad/codenames.csvAlexander Couzens
Collect all known codenames for thinkpads. Change-Id: Iae44ceb29675511ec562c275e750087eca5d2f27 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/21364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-03Documentation/Intel/vboot: Fix spelling of *following*Paul Menzel
Change-Id: I26cf3cb049fb5520c59316ff7397b0bcfe6ee48d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-05Documentation: Update Lesson2.mdEvelyn Huang
Update Lesson2.md to include information about updating a commit after it has been pushed to the remote repository. Change-Id: Iebf86113b13d859d9c9e3db51e22ea44cb1144f6 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10Documentation: Add binary extraction documentationLogan Carlson
Added documentation on how to extract binaries from a ROM image, including: - Using ifdtool to extract binaries. - Using cbfstool to extract binaries. - Changing menuconfig to use the extracted binaries. Change-Id: Ia31b01afc66789f95c7d21a0d41b532bc19a6430 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/20753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-01Documentation: Create Lesson2.mdEvelyn Huang
Lesson 2 goes over: -Setting up an account on gerrit -Cloning coreboot -Submiting a commit using git Change-Id: I756b273cf832fc014ba2077a5a4fe4d8009aae6d Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-12Documentation: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Unfortunately, some external websites and projects are spelling coreboot with an uppercase C, so references to those pages can't be changed without breaking the link. Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-06Documentation: Describe libgfxinit hook-upNico Huber
Change-Id: Ieeb53a1694193cd19b5e9aa5bee25e36a60e56bd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-25util/hugo: Add framework to build www.coreboot.org/DocumentationPatrick Georgi
www.coreboot.org/Documentation is now built with hugo (www.gohugo.io) based on files in this repo's /Documentation directory. Also clarify that new additions to Documentation are under CC-BY 4.0 terms. Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/19881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-05-03Documentation/Intel: Add vboot documentationLee Leahy
Add documentation which describes how to build and sign a coreboot image which enables vboot. TEST=None Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01Documentation: Add technote/design doc for mitigating ReBAR issuePatrick Georgi
Change-Id: Icba9d7910dfd46f32a2c46b6fd064a9cc8e3beac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-11Documentation: Reflow Kconfig.mdMartin Roth
The original document was written and committed with no regard to line lengths. This makes it easier to write. Now it needs to be easier to read, so wrap the lines at 80 characters where possible. - A couple of headings had to be rewritten to keep them under 80 characters. This required the addition of a new paragraph that had the old header. - Remove URL text that was just duplicating the URL. - All other text is the same, just wrapped. Change-Id: I44833c28750714fccb87296868c1ff78ab7f1d07 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19076 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-04Documentation/core: Update Kconfig documentationMartin Roth
- Remove document history. Since the document is now stored in git, this is no longer needed. - Fix spacing for the kconfig_lint help output - Add license information to the bottom of the document. Change-Id: I9854602a6ad9b4a99bf3988e1d7662b3b426e608 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19075 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-23Documentation: Add doxygen_platform targetMartin Roth
Create a doxygen target that builds documentation just for the platform that is currently selected in Kconfig. This gives us something that is much more useful to most people. Change-Id: I25c3cdac2dd383b89df6389ba9011dac913a0a9b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15577 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-22arch/x86/acpigen: Provide helper functions for enabling/disabling GPIOFurquan Shaikh
In order to allow GPIOs to be set/clear according to their polarity, provide helper functions that check for polarity and call set/clear SoC functions for generating ACPI code. BUG=None BRANCH=None TEST=Verified that the ACPI code generated remains the same as before for reef. Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-13Documentation: Add Kconfig documentMartin Roth
Change-Id: I99ca65343d52e99611644c0c65f4b7feb5c58436 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16947 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2016-10-29Documentation: Add documentation for GPIO toggling in ACPI AMLFurquan Shaikh
This document provides information about the different functions that a driver can use for generating ACPI code for toggling GPIO. These functions are expected to be implemented by the SoC. It also defines the different constraints on use of Local variables in ACPI code while implementing these functions. BUG=chrome-os-partner:55988 Change-Id: Ibc03d766afb6d7b75bc0dc9f79920b561f1c4a78 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-30Documentation/Intel/Soc: Update Quark FSP build instructionsLee Leahy
Update the FSP build instructions for Quark: * Discuss multiple types BRANCH=none BUG=None TEST=Build Quark FSP using new instructions Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-12Documentation: add start of documentation of the build systemPatrick Georgi
Change-Id: Ic4a4b4d71852bfe0b1fc52373e88d0a53b145844 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16150 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28Documentation: Capitalize RAM, ROM and ACPIElyes HAOUAS
Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15927 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-12Documentation: Fix doxygen errorsMartin Roth
Change-Id: I195fd3a9c7fc07c35913342d2041e1ffef110466 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15549 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-08soc/intel/quark: Pass in the memory initialization parametersLee Leahy
Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08Documentation/Intel: Add feature documentation tableLee Leahy
Add table containing feature documentation: * Feature name with link to specification or documentation * Linux utility name with link to utility documentation * EDK-II utility name with link to utility documentation Change-Id: Ie33d8563320697c12b34974286bffcadf92c016e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15256 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08Documentation: Add index.htmlLee Leahy
Add the initial index.html file. The web server is currently not converting .md files into html. Instead they are being downloaded in their raw .md file format. Use the index.html file to enable the web server to find and process the file. TEST=None Change-Id: I27334ccacdb34b56946a9061132acf2808d32175 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15218 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12Documentation/Intel/Board: Update the Galileo checklistLee Leahy
Update the Galileo board implementation checklist. TEST=Build and run on Galileo Gen2 Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15137 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02Documentation/Intel/Board: Add Galileo checklistLee Leahy
Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Documentation/Intel/Board: Add analog switch linkLee Leahy
Add link for TI TS5A23159 specification. TEST=None Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15003 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18Documentation/Intel: Update the documentationLee Leahy
index.html: * Separate the sections on the main page * Move the documentation links to the main page * Add links for FSP 1.0 and 2.0 specifications * Add link for UEFI specifications * Add link to MinnowBoard MAX coreboot fsp1_1.html: * Use Integration instead of Documentation SoC/quark.html: * Move documentation to main page * Update build instructions for CorebootPayloadPkg * Remove FatPkg since it is now part of edk2 tree * Add source location for QuarkFspPkg * Add build instructions for QuarkFspPkg TEST=None Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14882 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-11lib: remove FLASHMAP_OFFSET config variableAaron Durbin
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-21Documentation: x86 MTRR setup, TempRamExit and MTRR loadingLee Leahy
Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation/Intel: Add more Galileo Gen2 linksLee Leahy
Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation: x86 shadow ROM disableLee Leahy
Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07Documentation/Intel: Add EDK-II linksLee Leahy
Add a link to the "Driver Writer's Guide" and a link to the "EDK II firmware for Intel Quark SoC X1000" document. TEST=None Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13893 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-07Documentation/Intel: Making a bootable SD cardLee Leahy
Add a link to "Making a bootable SD card" TEST=None Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29Documentation/Intel: More CorebootPayloadPkg documentationLee Leahy
Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29Documentation/Intel: Add ACPI link and more FADT documentationLee Leahy
Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24Documentation/Intel: Add minimal APCI and TempRamExit documentationLee Leahy
Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructionsLee Leahy
Update the build instructions for CorebootPayloadPkg to target the Galileo Gen2 platform. TEST=Build and run on the Galileo Gen2 platform. Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-19Documentation: x86 device tree processing and memory mapLee Leahy
Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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