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2020-01-23Documentation: link asus p5q on mainboard pageFelix Held
Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-21mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)Ivan Vatlin
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-20Documentation/superio: add generic PNP device documentationFelix Held
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-18documentation: Add documentation on setting up mainboard GPIOsTim Wawrzynczak
The new documentation describes typical ways that mainboards will set up their GPIOs, as well as the distinction between "early" and "normal" GPIOs. It also describes the typical properties that GPIO configuration will cover. Change-Id: I279eec4ed2bb0248a2bdb363fb73b40b8272267f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-01-14Documentation: document non-Docker sphinx installation and usageFelix Held
Also update the known-good versions of the needed tools. Change-Id: I0f63860beb0a8a00360752318236e302c7170977 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10{Documentation,soc/intel}: Fix typoElyes HAOUAS
Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09acpi: Be more ACPI compliant when generating _UIDPatrick Rudolph
* Add function to generate unique _UID using CRC32 * Add function to write the _UID based on a device's ACPI path ACPI devices that have the same _HID must use different _UID. Linux doesn't care about _UID if it's not used. Windows 10 verifies the ACPI code on boot and BSODs if two devices with the same _HID share the same _UID. Fixes BSOD seen on Windows 10. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-26Doc/tutorial/part2.md: Align headings with part1.mdAngel Pons
Substitute `Part` with `Step` on this file's headings and use present tense instead of gerund. Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/tutorial/part1.md: Fix minor formatting issuesAngel Pons
Make sure all titles are capitalized, and add a missing period. Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/index.md: Fix a typoAngel Pons
Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-26Doc/releases/checklist.md: Correct some inconsistenciesAngel Pons
Use periods on every element of a list, and make `IRC` uppercase. Also, correct a grammar mistake that slipped through. Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-12-22superio/common: Add more ACPI methodsPatrick Rudolph
* Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-16Documentation: Extend release checklist (list to-be deprecated boards)Patrick Georgi
Make it part of the release process to note not only what config flags / code properties etc will be deprecated, but to also spell out which boards would be affected at the time of the release. Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD sectionAngel Pons
Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-12Documentation: Fix EC type for facebook and portwell boardsWim Vervoorn
Board description contained incorrect EC type. Change EC type to ITE8528 BUG=N/A TEST=build Change-Id: Ib5af79fb00bfdfc5dbe001b60010a74bddc696e2 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12Documentation: enable ditaa integrationPatrick Georgi
For prettier diagrams: http://ditaa.sourceforge.net/ Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-11Documentation: Fix table and layoutPatrick Georgi
The table wasn't pretty enough so sphinx complained, while the second paragraph had trailing whitespace, could be wrapped differently and also came with a typo. Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-10Documentation: Describe how to deal with snooping https proxiesPatrick Georgi
Disabling SSL verification is far from optimal, but depending on the circumstances may be the most practical way, so describe how to do that instead of leaving users confused. It's also not _that_ bad because git's hashing scheme should uncover most attempts to tamper with code, either when checking signed tags or when people push (and see lots of modified commits). State the command in a way that isn't conductive to careless copy & paste. Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-09Documentation: Move ACPI documentation in a subindexArthur Heymans
Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09Documentation: Remove redundant 'documentation'Arthur Heymans
We are already in documentation so it should be obvious that other links point to other documentation. Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06mb/facebook/monolith: Add Facebook MonolithWim Vervoorn
The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-29Documentation/4.12-relnotes.md: Add SMMSTORE as production readyArthur Heymans
Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29Documentation: Add SMMSTORE documentationArthur Heymans
This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-28Documentation: Rework staging and commit informationDavid Hendricks
This patch does two things: - The CLI and Git Cola sections contained some duplicated information about pushing patches, which is now factored out into its own section. - The draft workflow is now disabled, so that part has been reworded to describe how to submit a private patch. Signed-off-by: David Hendricks <david.hendricks@gmail.com> Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22Documentation/releases: Update checklistPatrick Georgi
Having the release notes mostly ready one week before the release allows for better review. Some statistics, the actual release date and commit ID can only be filled in on release day, but there's a tried & true technique for that: placeholders. It's also a nice touch to have the release notes of a release within its source tarballs, so push them right before creating the release (since changes in Documentation/releases won't break coreboot in any way). Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: Drop reference to piratenpadPatrick Georgi
Piratenpad is dead. Change-Id: Id9cfb68f6c6e05d1af2a526c817713a92220d370 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36958 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: Releasing includes announcing on the listPatrick Georgi
Change-Id: I063997d51a80b1b244a0cb35ae90446610ef2c21 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36975 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: 4.11 isn't "upcoming" anymore.Patrick Georgi
Change-Id: I7102519b171c3e5269fefaa66d12d605f5d9ddb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36974 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove imgtec/pistachio SoCJulius Werner
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation/releases: Finalize 4.11, start 4.12Patrick Georgi
Fill in some stats using our repo analysis scripts in util/release/, thank the contributors, add some prose about notable achievements since 4.10. Also start a new doc for 4.12. Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation: Remove duplicated entryPatrick Rudolph
The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation: Reword Supermicro X10SLM+-F datasheet referencesPaul Menzel
Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19docs: intel fsp: add memory retraining bug on SPS systemsMichael Niewöhner
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18Documentation/releases: Add libgfxinit changes in 4.11Nico Huber
Change-Id: Id7babdc9b1d908fa90ebac098a019615fa00b973 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18Documentation/releases: Add more c-env-bb platforms for 4.11Nico Huber
Change-Id: Ie5c83befc8e595016c63729a19e7e71438c996b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-15Documentation/mb/facebook/fbg1701.md: Update microcode blobFrans Hendriks
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15Documentation/mb/portwell/pq7-m107.md: Update microcode blobWim Vervoorn
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12Documentation: Add more entries to 4.11 release notesPatrick Georgi
Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11Documentation: Add some significant 4.11 release notesKyösti Mälkki
Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-11Documentation: Add some significant 4.11 release notesPatrick Rudolph
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-10arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans
Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07lib/cbfs: Add fallback to RO region to cbfs_boot_locateWim Vervoorn
With this change cbfs_boot_locate will check the RO (COREBOOT) region if a file can not be found in the active RW region. By doing so it is not required to duplicate static files that are not intended to be updated to the RW regions. The coreboot image can still be updated by adding the file to the RW region. This change is intended to support VBOOT on systems with a small flash device. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04Documentation: Add some significant 4.11 release notesKyösti Mälkki
Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2019-11-01Documentation: Fix typoPatrick Rudolph
The document isn't included in any toc-tree due to a typo. Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36540 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/portwell/m107: Add Kingston memory supportWim Vervoorn
Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-30Documentation: Add amd_blobs license agreement textMarshall Dawson
AMD has generated a simpler and more flexible license agreement for using proprietary precompiled binary images. The new agreement is intended to cover all blobs in the directory structure below where the license resides and eliminates any unique agreements previously provided for individual products. Add a description of the repo, as well as the license agreement it contains. Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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