coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2020-04-20	drivers/pc80/rtc: Drop CMOS_POST_EXTRA option	Kyösti Mälkki
	Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-19	arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE	Kyösti Mälkki
	If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-19	configs: add google/meep cros config as regression test	Patrick Georgi
	This config is a slightly stripped configuration of the Chromium OS configuration used in production. Apparently the bootblock fills up faster than usual on this device, resulting in address overflows. Add this config here so we'll notice early in the future. Change-Id: I3145bba63d32ddb9d00fd98d3cb774bf9ddd69a6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36923 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>