coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-04-23	configs: Add a target to buildtest the ivybridge mrc.bin bootpath	Arthur Heymans
2019-02-11	mb/intel/galileo: Drop the FSP1.1 option	Arthur Heymans
2018-10-23	soc/intel/apollolake: Add reset code to postcar stage	Patrick Georgi
2018-09-16	configs: add sercon port and disable pxe serial console for apu{2,3,4,5}	Piotr Król
2018-08-20	configs: Build test verbose BDK and FIT payload support	Patrick Rudolph
2018-08-17	configs: Add various common non-default mainboards	Patrick Rudolph
2018-05-19	configs: add PC Engines apu2 sample configuration	Piotr Król
2017-10-04	configs: Add intel/harcuvar FSP 2.0 sample configuration	Mariusz Szafranski
2017-06-20	configs: Add intel/galileo test configurations	Lee Leahy
2017-06-04	Kconfig: Add choice of framebuffer mode	Nico Huber
2017-01-20	configs/builder: Remove pre-defined VGA bios file	Philipp Deppenwiese
2017-01-18	configs/builder: Add Sandy/Ivy Bridge Thinkpad configurations	Philipp Deppenwiese
2016-12-09	configs: Add some sample default configuration files	Martin Roth