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path: root/payloads/libpayload/drivers/usb/ehci.c
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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01libpayload: Fix 16-bit read/write to PCI_COMMAND registerElyes HAOUAS
Change-Id: I34facbe0cbbdc91066799b586d96abca1599c509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40743 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17payloads: Fix typosElyes HAOUAS
Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-02libpayload/usb: Increase USB request timeout to 5 sKeith Short
Increase the timeout for USB requests to 5 seconds for all USB host controllers. Prior to this fix, the xCHI driver was detecting false timeouts during SET ADDRESS requests when nested downstream hubs were connected to the xHCI root hub. BUG=b:124730179 BRANCH=sarien TEST=Build libpayload and depthcharge on sarien/arcada. TEST=Without change replicate USB set address timeouts in depthcharge when dock and 4K monitor connected (which includes a total of 4 USB hubs). With timeout fix, depthcharge boots OS with no USB errors and the same USB topology. Note that this tests xHCI operation only. Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-09libpayload: Fix potential NULL pointer dereferenceFrancois Toguo
Found-by: Klockwork BUG=NONE TEST=Boot to OS on GLK Sparky Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d4636f0429de829e746909492c2f543026a02ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/32083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-23libpayload: Fill reg_base for debugging purposesPatrick Rudolph
Fill reg_base with physical register base address. Tested on Lenovo T500. Change-Id: If42135c8e10b70d5ac9626521abd9cca3cf40053 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18600 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15libpayload: Always set pciaddrPatrick Rudolph
For debugging purposes always set the pciaddr attribute. Tested on Lenovo T500. Change-Id: I83a0e7f7196ed251fa0becc4e56bef3ca68f20f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02payloads/libpayload: Add spaces around '=='Elyes HAOUAS
Change-Id: Ie1da925aceb01c2d21b472bf171000803004578f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-16libpayload: usb: dwc2: support split transactionYunzhi Li
With split transaction, dwc2 host controller can handle full- and low-speed devices on hub in high-speed mode. This commit adds support for split control and interrupt transfers BUG=None TEST=Connect usb keyboard through hub, usb keyboard can work BRANCH=None Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019 Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283282 Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-12libpayload: Fix passing BAR to EHCI driverPatrick Georgi
The EHCI driver never looked for the base address handed to it but instead used an uninitialized field for that information. Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-03-23libpayload: EHCI: Support root-hub TT featureJim Lin
If EHCI controller has TT (Transaction Translator) support in root-hub, then we need to keep control over this controller when USB keyboard (low-speed device) is connected to root-hub port. Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file (e.g. payloads/libpayload/configs/config.nyan_big) to support this feature. BUG=chrome-os-partner:32355 TEST=Tested on nyan_big platform. Press ESC+REFRESH+POWER keys on internal keyboard to power up. Press Left Arrow or Right Arrow on USB keyboard to switch between "English" and "Default Locale" in coreboot UI. Or unplug and plug in device and try again. Root hub <- low-speed USB keyboard Root hub <- full-speed hub <- low-speed USB keyboard Root hub <- high-speed hub <- low-speed USB keyboard Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220125 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload ehci: Use 64-byte aligned data structures for periodic transfersJim Lin
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says "Frame List Link pointers always reference memory objects that are 32-byte aligned." jwerner@chromium.org suggests setting it to be 64-byte aligned for consistency with other EHCI queue structures. BUG=chrome-os-partner:31993 TEST=Tested on nyan platform. Before adding patch, USB keyboard behind an external hub is not working to switch between "Default Locale" and "English" (after pressing ESC+REFRESH+POWER on embedded keyboard and later Left/Right-Arrow key on USB keyboard). Change-Id: Ie6259f2df20ae2618c2074e831fad087f227091d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23fc02e6ba3b17be4eaf18810ec6fc0d9c0e0b9a Original-Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218403 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: EHCI: Fix transaction error for interrupt transferJim Lin
Data toggle should be running like 0, 1, 0, 1, ... In the failed case (where a low-speed USB keyboard or km232 device is installed), data toggle will be running as 0, 1, 0, 1, ..., 1, 1. Therefore causing Halted or Transaction Error bit to be set in qTD Status field. BUG=None BRANCH=None TEST=Tested on nyan_kitty platform, firmware-kitty-5771.61.B branch. Attached USB keyboard or km232 device to root-hub port (same side as SD card slot). Made sure no transaction error after doing interrupt transfer. Change-Id: I576f3c583dae4c279a6e0e8ffdfce5abe463277d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64b0428aaab869e20f6720669e953acf82ecb846 Original-Change-Id: Ic2c0f95cff2ae6e314967b0b82231a962255f1a7 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233857 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload EHCI: Add memory barrier to EHCI driverFurquan Shaikh
EHCI driver accesses mmio space using regular struct pointers. In order to avoid any CPU re-ordering, memory barrier is required in async_set_schedule, especially for arm64. Without the memory barrier, there seems to be re-ordering taking place which leads to USB errors with some flash drives as well as transfer errors in netboot. BUG=chrome-os-partner:31533 BRANCH=None TEST=With the memory barrier introduced, netboot for ryu completes transfer without any error and finishes within 6-7 seconds. Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213917 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-13libpayload: usb: Fix up usb_shutdown() code pathsJulius Werner
This patch combines a few minor fixes and refactoring to the various host controller and root hub drivers to ensure they all do the right thing on a call to usb_exit(). It puts a usb_detach_device(0) call into detach_controller() so that the HCD doesn't need to remember to tear down the root hub itself, and makes sure all root hubs properly detach the subtree of devices connected to their ports first (as generic_hub and by extension XHCI had already been doing). It also fixes up some missing free() calls and replaces most 'ptr = malloc(); if (!ptr) fatal()' idioms with the new x(z)alloc(). BUG=chromium:343415 TEST=Tested EHCI on Big and OHCI, EHCI, and XHCI on Snow. Could not test UHCI (unless anyone volunteers to port coreboot to a ZGB? ;) ), but the changes are really tame. Original-Change-Id: I6eca51ff2685d0946fe4267ad7d3ec48ad7fc510 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193731 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5791b546e5a21a360d0c65888a5b92d5f48f8178) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I00138f0aeceb12ed721f7368c7788c9b6bee227d Reviewed-on: http://review.coreboot.org/7222 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10libpayload: ehci: Fix byte count in dump_td()Julius Werner
The dump_td() debug function in the EHCI stack incorrectly masks the amount of transferred bytes on output... the actual field is 15 bits wide (30:16). Let's just use the mask constant we already have for all the other code. Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174986 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 570077da7f16bbe2204b4a80790e4bd8fe1a2bd7) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14libpayload: Make EHCI driver cache-awareJulius Werner
This patch makes the EHCI driver work on ARM platforms which usually do not support automatic cache snooping. It uses the new DMA memory mechanism (which needs to be correctly set up in the Coreboot mainboard code) to allocate all EHCI-internal communication structures in cache-coherent memory, and cleans/invalidates the externally supplied transfer buffers in Bulk and Control functions with explicit calls as necessary. Old-Change-Id: Ie8a62545d905b7a4fdd2a56b9405774be69779e5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167339 (cherry picked from commit 322338934add36a5372ffe7d2a45e61a4fdd4a54) libpayload: ehci: Cache management is hard, let's go copying... It turns out that my previous commit to make the EHCI stack cache aware on ARM devices wasn't quite correct, and the problem is actually much trickier than I thought. After having some fun with more weird transfer problems that appear/disappear based on stack alignment, this is my current worst-case threat model that any cache managing implementation would need to handle correctly: Some upper layer calls ehci_bulk() with a transfer buffer on its stack. Due to stack alignment, it happens to start just at the top of a cache line, so up to 64 - 4 bytes of ehci_bulk's stack will share that line. ehci_bulk() calls dcache_clean() and initializes the USB transfer. Between that point and the call to dcache_invalidate() at the end of ehci_bulk(), any access to the stack variables in that cache line (even a speculative prefetch) will refetch the line into the cache. Afterwards any other access to a random memory location that just happens to get aliased to the same cache line may evict it again, causing the processor to write out stale data to the transfer buffer and possibly overwrite data that has already been received over USB. In short, any dcache_clean/dcache_invalidate-based implementation that preserves correctness while allowing any arbitrary (non cache-aligned) memory location as a transfer buffer is presumed to be impossible. Instead, this patch causes all transfer data to be copied to/from a cache-coherent bounce buffer. It will still transfer directly if the supplied buffer is already cache-coherent, which can be used by callers to optimize their transfers (and is true by default on x86). Old-Change-Id: I112908410bdbc8ca028d44f2f5d388c529f8057f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169231 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 702dc50f1d56fe206442079fa443437f4336daed) Squashed the initial commit and a follow up fix. Change-Id: Idf7e5aa855b4f0221f82fa380a76049f273e4c88 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.Julius Werner
The EHCI host controllers in Samsung Exynos SoC seem to be a little more picky than Intel ones. When they reach the dummy_qh in the periodic frame list, they try to access the next qTD pointer even though it's NULL, and run into a HostSystemError. This patch explicitly sets the Terminate bit on those pointers to mark them invalid. Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66884 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12libpayload: Make USB transfer functions return amount of bytesJulius Werner
The USB bulk and control transfer functions in libpayload currently always return 0 for success and 1 for all errors. This is sufficient for current use cases (essentially just mass storage), but other classes (like certain Ethernet adapters) need to be able to tell if a transfer reached the intended amount of bytes, or if it fell short. This patch slightly changes that USB API to return -1 on errors, and the amount of transferred bytes on successes. All drivers in the current libpayload mainline are modified to conform to the new error detection model. Any third party users of this API will need to adapt their if (...<controller>->bulk/control(...)) checks to if (...<controller>->bulk/control(...) < 0) as well. The host controller drivers for OHCI and EHCI correctly implement the new behavior. UHCI and the XHCI stub just comply with the new API by returning 0 or -1, but do not actually count the returned bytes. Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48308 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Updated the patch to support XHCI as well. Change-Id: Ic2ea2810c5edb992cbe185bc9711d2f8f557cae6 (cherry picked from commit e39e2d84762a3804653d950a228ed2269c651458) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6390 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-05libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.Gabe Black
When libpayload header files are included in the payload itself, it's possible that the payloads config settings will conflict with the ones in libpayload. It's also possible for the libpayload config settings to conflict with the payloads. To avoid that, the libpayload config settings have _LP_ (for libpayload) added to them. The symbols themselves as defined in the Config.in files are still the same, but the prefix added to them is now CONFIG_LP_ instead of just CONFIG_. Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65303 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6427 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-10libpayload: Drop obsolete setting of reg_base in [oex]hciNico Huber
Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6251 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Use unsigned long for BARs in *hci_init()Nico Huber
Using void* for physical addresses leads to much casting and confuses developers when to convert from physical to virtual addresses or the other way around. When using plain integers for physical addresses and pointers for virtual addresses things become much cleaner and we won't ever end up dereferencing a physical address. Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6244 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2013-12-21libpayload: Increase USB EHCI transfer timeoutJulius Werner
The EHCI driver defines a maximum transfer timeout of two seconds. The comments state that during tests the maximum amount of required transfer time was for the SCSI TEST_UNIT_READY command on certain devices. We have now observed a USB device (Patriot Memory 13fe:3100) that can NAK this command for slightly more than two seconds. It will also completely fail if the timeout hits, since it gets confused by the subsequent CSW retry/recovery mechanism and starts producing babble errors. This patch increases the timeout to three seconds to circumvent this problem. To test, boot a Falco from a red-black RageXT USB stick. Change-Id: I3c4fef468fb16eacc5a487d76d025a78fb450e27 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/4379 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-11-25libpayload: Add USB support for non-PCI controllersStefan Reinauer
Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 Reviewed-on: http://review.coreboot.org/4175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-13libpayload: Redirect USB slave init through controller driverPatrick Georgi
xHCI requires special treatment of set_address since it determines the device number itself (instead of the driver, as with the other controllers). The controller also wants to validate a chosen device configuration and we need to setup additional structures for the device and the endpoints. Therefore, we add three functions to the hci_t structure, namely: set_address() finish_device_config() destroy_device() Current implementation for the Set Address request moved into generic_set_address() which is set_address() for the UHCI, OCHI and EHCI drivers. The latter two are only provided as hooks for the xHCI driver. The Set Configuration request is moved after endpoint enumeration. For all other controller drivers nothing changes, as there is no other device communication between the lines where the set_configuration() call moved. Change-Id: I6127627b9367ef573aa1a1525782bc1304ea350d Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3447 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-26libpayload: Fix unused function warning in EHCI stackStefan Reinauer
The function dump_qh() was added a while back but never used. Hide it behind USB_DEBUG so it doesn't cause warnings when not debugging the USB stack. Change-Id: Idb3c7bb214895ef82676d181836a578bf161e8e0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2909 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-25libpayload: EHCI - detach controller in ehci_shutdown()Mathias Krause
It shouldn't be used any more as we're about to free() the memory behind the controller -- therefore detach it. Change-Id: I875322a9940570c51d412a7f3bfb6af4ea3b3764 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/2899 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber@secunet.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-13libpayload: Split EHCI bulk transfers on packet boundaries over qTDsJulius Werner
EHCI controllers see transfers as a queue of transfer descriptors (qTDs), each of which can represent an aligned area of up to 20KB. Each qTD is processed separately, which means that a single USB packet cannot span multiple qTDs. While this should not be a problem according to the specification, some USB storage devices seem to get confused when a packet in the middle of a transfer is smaller than the maximum packet size (512 bytes) due to falling on a qTD boundary. This patch aligns the total transfer length per qTD to 512 bytes to avoid that problem (any excess bytes will simply roll over to the next qTD). Change-Id: I0b5db07507699a3861b30c1a5ee774c45dda7fdd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/2651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: add support for 64-bit EHCI controllersVincent Palatin
Initialize the high part of the address and use 64-bit compatible descriptors. (waste a few bytes on 32-bit but should be harmless) Read USB stick on a SandyBridge system which has 64-bit EHCI. Change-Id: I59cc842459acecdde8f8bdd4795ebfeccb842c8f Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28libpayload: Check for completion more often in ehci_set_periodic_schedule.Gabe Black
This function was using mdelay in a loop to check for the completion of an USB controller operation. Since we're busy waiting anyway, we might as well wait only 1 us before checking again and potentially seeing the completion 999 us earlier than we would otherwise. Change-Id: I177b303c5503a0078c608d5f945c395691d4bd8a Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2522 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-01libpayload: add EHCI QH/qTD debuggingAnton Kochkov
Improve USB debugging for EHCI by adding dump_qh and enhacing dump_td to dump all queue chain and information. Change-Id: Ia8ecf19c6dac085cf9558bdf659a5e74ce332714 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/2053 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-12-18libpayload: Use usb_debug() to show USB messagesDave Frodin
Previously printf()'s were used to show USB messages which results in lots of USB information being shown when it isn't needed. This will now use the usb_debug() printing funtion that already exists in usb.h. Change-Id: I2199814de3327417417eb2e26a660f4a5557cb9f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2044 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-23libpayload: ehci: Prevent some race conditionsNico Huber
Prevent race conditions, when an interrupt-queue underrun occurred and the controller is currently working on our queue head or a transfer is still in progress. Change-Id: Ia14f80a08071306ee5d1349780be081bfacb206a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1902 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: Reduce error output from EHCINico Huber
Stalled transfers are not fatal, so don't spew on the console on every tiny failure. Change-Id: I175c1e83a6af09c1abbd43d045ed6dbf0c79f871 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1899 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: ehci: Fix warnings about discarded volatileNico Huber
We can trust free() and memset() to work correctly on volatile references, so cast volatile pointers to (void *) when calling them. Change-Id: Ieff7f78133b72f303349cca0a0ca3bbf37ec52bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1896 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-14libpayload: Add init() function to hci_t and rework uhci_reset()Nico Huber
uhci_reset() differs in semantics compared to the other HCI's reset() implementations. uhci_reset() does some initialization work after a controller reset. So move the initialization part to a new function, uhci_reinit(), which get's exported through a new entry in hci_t: hci_t.init(). Warning: This breaks code that relies on the current, special, counterintuitive behaviour of uhci_reset(). If one wants a working host controller after calling hci_t.reset(), he should call hci_t.init() afterwards. Change-Id: Ia7ce80865d12d11157645ce251f77f349f8e3c34 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Free usb host controller instance after shutdownNico Huber
All shutdown() implementations but ehci_shutdown() free the hci_t structure. This seems correct and the reference to the hci_t shouldn't be used after shutdown(), so do it in ehci_shutdown(), too. Change-Id: Ie3506d769e73007735f3211710734a5f0107e43a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1849 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09[PATCH] libpayload: Implement EHCI reset functionAnton Kochkov
Added ehci_reset() function to do a full reset of the host controller Change-Id: Ia48db8462ebbb8f260813eb6ba8349d002c4678b Signed-off-by: Anton Kochkov <a.kochkov@securitycode.ru> Reviewed-on: http://review.coreboot.org/1814 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07libpayload: Turn the "debug" #define into the usb_debug static inline function.Gabe Black
The "debug" macro used internally in the libpayload USB subsystem was very generically named and would leak into consumers of the library that included usb.h directly or indirectly. This change turns that #define from a macro into a static inline function to move away from the preprocessor, and also renames it to usb_debug so it's less likely to collide with something unrelated. Change-Id: I18717df111aa9671495f8a2a5bdb2c6311fa7acf Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1738 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-08-23libpayload: add controller type in usbdev_hcAnton Kochkov
Add controller type (UHCI, OHCI, EHCI or XHCI) into usbdev_hc (hci_t) struct, so now we know which type selected controller have. It needed to access controller specific data, if access usb tree outside of libpayload (e.g. in payload intself) Change-Id: I7df947bbb56a50d0d792ccd4d3a6b021ee95e2ea Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21libpayload: Add dummy queue heads to EHCI interrupt frame listNico Huber
This introduces a dummy queue head in the interrupt frame list of the EHCI host controller. It's a workaround for broken controllers which follow pointers from this list even if the terminate bit is set. Fortunately, they do honor the bit in queue heads and having an empty QH in the list doesn't violate the standard. The linux kernel has a similar workaround for AMD SB700, SB800, and Hudson-2/3 platforms. We observed this bug with an AMD SB600. Change-Id: Ibbb66dea5fddc89c7995a24d746bedf6bfa887be Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1124 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Add interrupt-queue underrun recovery to EHCINico Huber
If the queue of an interrupt transfer runs out, we have to reset the queue head. This also introduces the use of a spare transfer descriptor (TD) in interrupt queues, which assures, that a processed TD won't be reused until the host controller has written it back from his overlay. Change-Id: Id0eeb2808b77f1c187f164eb34bd66f8f399938b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1123 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-21libpayload: Adjust timeout in EHCI driverNico Huber
Tested with a bunch of usb flash sticks. The slowest non-TUR (test unit ready) turn around took about 1.3s, so this commit increases the timeout to 2s. Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21libpayload: reg_base reading for USB EHCI driverAnton Kochkov
Added reading registers base address for USB EHCI driver in ehci_init() function. Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-08libpayload: Add timeouts in the EHCI USB driverNico Huber
We should always have some timeout when we wait for the hardware. This adds missing timeouts to the EHCI driver. Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1077 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Add support for interrupt transfers in EHCINico Huber
This adds support for usb interrupt transfers in the EHCI driver. Split transactions are supported, so this enables support for HID keyboards devices over hubs in high-speed mode. Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07libpayload: Add support for split transactions in EHCINico Huber
With split transactions, the EHCI host controller can handle full- and low-speed devices on hubs in high-speed mode. This adds support for split transactions for control and bulk transfers. Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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