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Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu
Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510
Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:31634
BRANCH=None
TEST=test_exc generates and handles exceptions properly
Change-Id: If3ecab93be6d02942b52960ec97edc687bedf64b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bba2caae0bd436ba9e5215f5d8606ce8c4987c98
Original-Change-Id: I4abe8a0e426eab2532852179dbb32505353cd0a1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214609
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board; works as
expected
BRANCH=none
Change-Id: I368494f388b82969dda0ce73a38824791efce616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace
Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245386
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected.
BRANCH=none
Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8745
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This adds CB_TAG_RAM_CODE and an entry to sysinfo_t.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=Built and booted on pinky w/ depthcharge patch and saw that
/proc/device-tree/firmware/coreboot/ram-code contains correct
value
Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f
Original-Reviewed-on: https://chromium-review.googlesource.com/231132
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8755
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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CQ-DEPEND=CL:228856
BUG=chrome-os-partner:33676
BRANCH=None
TEST=Compiles and boots to kernel prompt. ramoops console log verified after
causing kernel to fault.
Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6
Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/228742
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The WiFi calibration blob saved in the CBMEM by coreboot needs to be
visible by depthcharge to supply it to the kernel.
BRANCH=storm
BUG=chrome-os-partner:32611
TEST=none yet
Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f
Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225506
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8753
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully
Change-Id: If89e7a537e6f0321ef43641c924a8ef057f51147
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f39cdbf68b674ef9b65441038ec79548145a88d
Original-Change-Id: Ie9904bf8abfa5ce1d87a586e5b08eb320793942f
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217821
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8790
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These functions are usually provided by gcc lib, which is not supposed
to be included on embedded platforms. This patch adds a no thrills C
implementation.
Other than MIPS platforms are happy using the gcc library provided
implementation, but in case of Chrome OS MIPS toolchain the libraries
are compiled with the small GOT, such that the entire data segment
does not fit.
With this implementation mips, arm and x86 targets build fine.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=checked the logic by incorporating this code into a C file and
running a loop continuously comparing random inputs' division and
left and right shift results.
The test ran for extended periods of time without failure.
Change-Id: I468acd2fdbcdd493a76758a394e79cad35f9535a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2cc5f8668dd2609408af8da5a74c5a3d063fc0d3
Original-Change-Id: Ib46616d7eb0b2b497199270057514f730bb1cb0b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Pass MAC addresses found in coreboot table into lib_sysinfo.
BUG=chrome-os-partner:32152
TEST=with all changes in place MAC addresses are properly inserted
into the kernel device tree.
Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78
Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219444
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There are three instances of coreboot.c in libpayload. for x86, arm
and arm64 architectures. The arm and arm64 instances are exactly the
same. The differences with the x86 instance are as follows:
- a very slightly different set of coreboot table tags is parsed (one
tag added and two removed)
- instead of checking a fixed address if it contains the coreboot
table, the x86 version iterates over two address ranges.
This patch refactors the module, leaving architecture specific
processing in arch subdirectories and moving the common code into
libc.
BUG=none
TEST=none yet
Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598
Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210770
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Make board ID value supplied in the coreboot table available to the
bootloader on all three architectures.
BUG=chrome-os-partner:30489
TEST=none yet
Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b
Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210430
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds a simple function to convert a string in UTF-16LE
to ASCII.
TEST=Ran against a string found in a GPT with the intended outcome
BRANCH=none
BUG=none
Change-Id: I94ec0a32f5712259d3d0caec2233c992330228e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1104db8328a197c7ccf6959a238277f416a2113a
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Change-Id: I50ca5bfdfbef9e084321b2beb1b8d4194ca5af9c
Original-Reviewed-on: https://chromium-review.googlesource.com/231456
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8733
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add support for memory barriers in arch {arm,arm64,x86}. This is required to
force strict CPU ordering. Definitions are based on FREEBSD atomic.h
definitions.
BUG=chrome-os-partner:31533
BRANCH=None
TEST=Memory barriers tested with ehci driver on arm64
Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552
Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213916
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Similarly to xzalloc() and xmalloc() provide an xmemalign() function
to do the approriate assertions on allocation failure.
BUG=None
BRANCH=None
TEST=Built and booted using xmemalign().
Change-Id: I59579d9ee973af3bb34037b7df5b1024b60e348d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3001822656024dbfc34d6b849a0245274b8c0f46
Original-Change-Id: Ie307d4c9c1882bba25745afe38455f2682303e37
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242455
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8728
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add OpenBSD's header-only implementation of some
basic data structures, imported from
src/sys/sys/queue.h, revision 1.38
(all whitespace errors kept verbatim)
Unlike home-grown solutions they likely handle
all corner cases correctly from the start and
unlike Linux's solution it's properly documented
(see OpenBSD's LIST_INIT(3)) and also BSD-l.
BRANCH=none
BUG=none
TEST=none
Change-Id: I89ae4df0c73662c355537283e7559af03a8b99a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f89e0316e6d68158c689bed4b1bdfe168c1449a
Original-Change-Id: Ie08a567851a2f07cbd2ac80ba31d8bca9844937d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8727
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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setbits_le32() is not really arch-specific... the arch-specific part of
accessing memory is wrapped by readl() and writel(), and the endianness
can be accounted for with the right macros. Generalize the definitions,
add a be32 version and move them to endian.h so that all platforms can
use them. Also include endian.h from libpayload.h so we won't update any
payload's old use of the macros (endianness is something useful enough
to always have avalable anyway, and shouldn't clash with other things).
This also fixes a bug where these macros would only be available if
libpayload-config.h had been independently included before.
Also fix a bug with readl() macros on all archs where they refused to
work on const pointers (which they should).
CQ-DEPEND=CL:208712
BUG=None
TEST=Stuff still compiles. Built and booted on Storm.
Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208713
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8
Reviewed-on: http://review.coreboot.org/8129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Correct function names to make them consistent with depthcharge calling
convention
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I0fd8f7f929c3fe268710362d1fc19f9e15c4a23b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/204423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 36008e728b840d85bb98225c7bb1420b993181de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4b446da8f2c273385ee885c4870966e18ba2a7a6
Reviewed-on: http://review.coreboot.org/8122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds the ability to attach a GDB host through the UART to a
running payload. Libpayload implements a small stub that can parse and
respond to the GDB remote protocol and provide the required primitives
(reading/writing registers/memory, etc.) to allow GDB to control
execution.
The goal of this implementation is to be as small and uninvasive as
possible. It implements only the minimum amount of primitives required,
and relies on GDB's impressive workaround capabilities (such as
emulating breakpoints by temporarily replacing instructions) for the
more complicated features. This way, a relatively tiny amount of code on
the firmware side opens a vast range of capabilities to the user, not
just in debugging but also in remote-controlling the firmware to change
its behavior (e.g. through GDBs ability to modify variables and call
functions).
By default, a system with the REMOTEGDB Kconfig will only trap into GDB
when executing halt() (including the calls from die_if(), assert(), and
exception handlers). In addition, payloads can manually call gdb_enter()
if desired. It will print a final "Ready for GDB connection." on the
serial, detach the normal serial output driver and wait for the commands
that GDB starts sending on attach.
Based on original implementation by Gabe Black <gabeblack@chromium.org>.
BUG=chrome-os-partner:18390
TEST=Boot a GDB enabled image in recovery mode (or get it to hit a
halt()), close your terminal, execute '<toolchain>-gdb --symbols
/build/<board>/firmware/depthcharge_gdb/depthcharge.elf --directory
~/trunk/src/third_party/coreboot/payloads/libpayload --directory
~/trunk/src/platform/depthcharge --directory
~/trunk/src/platform/vboot_reference --ex "target remote
<cpu_uart_pty>"' and behold the magic.
(You can also SIGSTOP your terminal's parent shell and the terminal
itself, and SIGCONT them in reverse order after GDB exits. More
convenient wrapper tools to do all this automatically coming soon.)
Original-Change-Id: Ib440d1804126cdfdac4a8801f5015b4487e25269
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202563
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 9c4a642c7be2faf122fef39bdfaddd64aec68b77)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9238b4eb19d3ab2c98e4e1c5946cd7d252ca3c3b
Reviewed-on: http://review.coreboot.org/8119
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch makes some slight changes to the exception hook interface.
The old code provides a different handler hook for every exception
type... however, in practice all those hook functions often need to look
very similar, so this creates more boilerplate than it removes. The new
interface just allows for a single hook with the exception type passed
as an argument, and the consumer can signal whether the exception was
handled through the return value. (Right now this still only supports
one consumer, but it could easily be extended to walk through a list of
hooks if the need arises.)
Also move the excepton state from an argument to a global. This avoids a
lot of boilerplate since some consumers need to change the state from
many places, so they would have to pass the same pointer around many
times. It also removes the false suggestion that the exception state was
not global and you could have multiple copies of it (which the exception
core doesn't support for any architecture).
On the ARM side, the exception state is separated from the exception
stack for easier access. (This requires some assembly changes, and I
threw in a few comments and corrected the immediate sigils from '$' to
the official '#' while I'm there.) Since the exception state is now both
stored and loaded through an indirection pointer, this allows for some
very limited reentrance (you could point it to a different struct while
handling an exception, and while you still won't be able to return to
the outer-level exception from there, you could at least swap out the
pointer and return back to System Mode in one go).
BUG=chrome-os-partner:18390
TEST=Made sure normal exceptions still get dumped correctly on both
archs.
Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202562
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
*** Squashed to prevent build failures. ***
libpayload: align arm64 with new exception handling model
The exception handling was previously updated, however the
arm64 changes raced with hat one. Make the arm64 align with
the new model. Without these changes compilation will fail.
BUG=None
BRANCH=None
TEST=Can build libpayload for rush.
Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204402
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e
Reviewed-on: http://review.coreboot.org/8117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds a console_kill_output_driver() function, which can
remove a previously registered output driver. This is mostly useful when
you overlay some output channel over another, such as when the GDB stub
takes direct control of the UART (and thus has to get rid of the
existing serial output driver).
BUG=chrome-os-partner:18390
TEST=None
Original-Change-Id: I6fce95c22fd15cd321ca6b2d6fbc4e3902b1eac3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202561
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 87680a246429d24e99b7b477b743c357f73b752c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I50001cee4582c962ceedc215d59238867a6ae95a
Reviewed-on: http://review.coreboot.org/8116
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Basic support for arm64 is enabled in libpayload.
Features added:
1) mem* operations in assembly.
2) Basic exception handling and support for testing exceptions.
3) Caching support.
Tested with arm64-generic board compilation.
BUG=None
BRANCH=None
TEST=Compilation successful
Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/187067
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251
Reviewed-on: http://review.coreboot.org/8063
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some drivers being ported to depthcharge use io bit manipulation
macros. The libpayload include file seems the most appropriate place
to keep these macros in. There is no common io.h file across
architectures, the x86 version could be added later if required.
BUG=chrome-os-partner:27784
TEST=observed ipq806x SPI driver deptcharge port (WIP) compile properly.
Original-Change-Id: I33f3be072faefce293c871f7e3bc3b2e6bc38ffe
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202559
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit ad18a605b4d0ec3251c1614e7358b42aa6b5c45a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8656e12af20ce4cf11d771942e8fe7d4eb2a560d
Reviewed-on: http://review.coreboot.org/8062
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The earlier compilation warning fix (chromium 7e4aa17) incorrectly
assumed that selfboot() is a function defined in the cbfs driver.
This is a commonly available function, it should not come from cbfs.h.
BUG=none
TEST=the following build command succeeds:
rambi storm nyan_big
Original-Change-Id: I3ef49d849168ad9dc24589cbd9ce7382052345bd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201386
(cherry picked from commit d5090e8410530f41b9fd33e2caa1d8aa25438105)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8404fb52112b391982f954a6d06fe4b451dfcb8a
Reviewed-on: http://review.coreboot.org/8003
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Fix pointer related casts since this can create a problem for 64-bit systems.
BUG=None
BRANCH=None
TEST=Compiled successfully for link, nyan using emerge-* libpayload
Original-Change-Id: I4cbd2d9f1efaaac87c3eba69204337fd6893ed66
Original-Reviewed-on: https://chromium-review.googlesource.com/199564
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 914b118a64b0691aeca463dff24252db9c24109e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I11f070ed5d3eddd8b9be30c428cb24c8439e617b
Reviewed-on: http://review.coreboot.org/7905
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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When emerging libpayload a warning is generated about selfboot() being
defined without a prior prototype.
Add cbfs.h when CBFS use if compiled fixes the warning.
BUG=none
TEST=build rambi storm nyan_big
verify that there is no compilation warnings thrown any more
Original-Change-Id: Ic9cb5571f708bb006a0d477e451fd1f3b3eb833f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200099
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 7e4aa17936b70dd08f58b3a55c6db55ea03709d7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie3baaaca82fb6ec432860c638acb2a3ef9451469
Reviewed-on: http://review.coreboot.org/7909
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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The calling convention of payload entry function is different by architecture.
For example, X86 takes no arguments and ARM needs first param to be a
cb_header_ptr*.
To help payloads load and execute other payloads easily and correctly, we should
provide the selfboot() function in libpayload, using same prototype as defined
in coreboot environment.
BUG=none
TEST=emerge-nyan libpayload # pass
BRANCH=none
Original-Change-Id: I8f1cb2c0df788794b2f6f7f5500a3910328a4f84
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199503
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 1e916cf021ce68886eb9668982c392eadedc7b7e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7279ef27f49ef581d25a455dd8f1f2f7f1ba58cb
Reviewed-on: http://review.coreboot.org/7907
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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I always thought the support for multiple logical SCSI units in the USB
mass storage class was a dead feature. Turns out that it's actually used
by SD card readers that provide multiple slots (e.g. one regular sized
and one micro-SD). Implementing perfect support for that would require a
major redesign of the whole MSC stack, since the one device -> one disk
assumption is deeply embedded in our data structures.
Instead, this patch implements a poor man's LUN support that will just
cycle through all available LUNs (in multiple calls to usb_msc_poll())
until it finds a connected device. This should be reasonable enough to
allow these card readers to be usable while only requiring superficial
changes.
Also removes the unused 'protocol' attribute of usb_msc_inst_t.
BRANCH=rambi?,nyan
BUG=chrome-os-partner:28437
TEST=Alternatively plug an SD or micro-SD card (or both) into my card
reader, confirm that one of them is correctly detected at all times.
Original-Change-Id: I3df4ca88afe2dcf7928b823aa2a73c2b0f599cf2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198101
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 960534a20e4334772c29355bb0d310b3f41b31ee)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I39909fc96e32c9a5d76651d91c2b5c16c89ace9e
Reviewed-on: http://review.coreboot.org/7904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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We recently changed the USB stack to detach devices aggressively that we
don't intend to use. This alone is not really a problem, but it
exarcerbates the fact that our device detachment itself is not very
good. We destroy any local info about the device, but we don't properly
disable the offending port. The device keeps thinking that it's active,
and if we later try to reuse that device address for another device
things become confused.
The real fix would be to properly disable all ports that we don't intend
to use. Unfortunately, this isn't really possible in our current
device/hub polymorphism structure, and I don't want to hack a new
disable_port() callback into usbdev_t that really doesn't belong there.
We will only be able to fix this cleanly after we ported all root hubs
to the generic_hub interface.
Until then, an easy workaround is to just avoid reusing addresses as
long as possible. This is firmware, so the chance that we'll ever run
through 127 devices is really small in practice. Even if we ever fix the
underlying issue, it's probably a smart precaution to keep.
BRANCH=nyan,rambi
BUG=chrome-os-partner:28328
TEST=Boot from a hub that has an "unknown" device in an earlier port
than the stick you want to boot from, make sure you can still boot.
Original-Change-Id: I9b522dd8cbcd441e8c3b8781fcecd2effa0f23ee
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197420
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 28b48aa69b55a983226edf2ea616f33cd4b959e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id4c5c92e75d6b5a7e8f0ee3e396c69c4efd13176
Reviewed-on: http://review.coreboot.org/7881
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The console output driver framework in libpayload is currently built on
the putchar primitive, meaning that every driver's function gets called
one character at a time. This becomes an issue when we add drivers that
could output multiple characters at a time, but have a high constant
overhead per invocation (such as the planned GDB stub, which needs to
wrap a special frame around output strings and wait for an
acknowledgement from the server).
This patch adds a new 'write' function pointer to the
console_output_driver structure as an alternative to 'putchar'. Output
drivers need to provide at least one of the two ('write' is preferred if
available). The CBMEM console driver is ported as a proof of concept
(since it's our most performace-critical driver and should in theory
benefit the most from less function pointer invocations, although it's
probably still negligible compared to the big sprawling mess that is
printf()).
Even with this fix, the problem remains that printf() was written with
the putchar primitive in mind. Even though normal text already contains
an optimization to allow multiple characters at a time, almost all
formatting directives cause their output (including things like
padding whitespace) to be putchar()ed one character at a time.
Therefore, this patch reworks parts of the output code (especially
number printing) to all but remove that inefficiency (directives still
invoke an extra write() call, but at least not one per character). Since
I'm touching printf() core code anyway, I also tried to salvage what I
could from that weird, broken "return negative on error" code path (not
that any of our current output drivers can trigger it anyway).
A final consequence of this patch is that the responsibility to prepend
line feeds with carriage returns is moved into the output driver
implementations. Doing this only makes sense for drivers with explicit
cursor position control (i.e. serial or video), and things like the
CBMEM console that appears like a normal file to the system really have
no business containing carriage returns (we don't want people to
accidentally associate us with Windows, now, do we?).
BUG=chrome-os-partner:18390
TEST=Made sure video and CBMEM console still look good, tried printf()
with as many weird edge-case strings as I could find and compared serial
output as well as sprintf() return value.
Original-Change-Id: Ie05ae489332a0103461620f5348774b6d4afd91a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196384
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ab1ef0c07736fe1aa3e0baaf02d258731e6856c0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I78f5aedf6d0c3665924995cdab691ee0162de404
Reviewed-on: http://review.coreboot.org/7880
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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`*memory` is not changed in `hexdump()` and just read so make it
`const`.
Change-Id: I9504d25ab5c785f05c39c9a4f48c21f68659a829
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5403
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some
chars, then verified they can be read from the pointer returned.
BUG=chrome-os-partner:25587
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88
Original-Reviewed-on: https://chromium-review.googlesource.com/188894
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529
Reviewed-on: http://review.coreboot.org/7658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use the SPSR to extract and inject CPSR values when an exception happens and
pass that information to exception hooks.
The register structure GDB expects when using its remote protocol has a spot
for the CPSR.
BUG=None
TEST=Built and booted on link, nyan.
BRANCH=None
Original-Change-Id: Id950fb09d72fb0f81e4eef2489c0849ce5dd8aca
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/180253
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8e7014f24a580f84c91fa7b0369dfa922918adcc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I49357fb6a65edeff7a9a48d54254308a6b0efdb7
Reviewed-on: http://review.coreboot.org/7657
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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To support a GDB stub, it will be necessary to trap various exceptions which
will be used to implement breakpoints, single stepping, etc.
BUG=None
TEST=Built and booted on Link with hooks installed and saw that they
triggered when exceptions occurred. Built and booted on nyan.
BRANCH=None
Original-Change-Id: Iab659365864a3055159a50b8f6e5c44290d3ba2b
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/179602
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8db0897b1ddad600e247cb4df147c757a8187626)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5e7f724b99988cd259909dd3bd01166fa52317ec
Reviewed-on: http://review.coreboot.org/7656
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch changes the ENTRY() macro in asm.h to create a new section
for every assembler function, thus providing dcache_clean/invalidate_all
and friends with the same --gc-sections goodness that our C functions
have. This requires a few minor changes of moving around data (to make
sure it ends up in the right section) and changing some libgcc functions
(which apparently need to have two names?), but nothing serious.
(You may note that some of our assembly functions have data, sometimes
even writable, within the same .text section. This has been this way
before and I'm not looking to change it for now, although it's not
totally clean. Since we don't enforce read-only sections through paging,
it doesn't really hurt.)
BUG=None
TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not
output into any binary anymore since no one actually uses it.
Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/183891
(cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9
Reviewed-on: http://review.coreboot.org/7451
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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This patch changes several cache-related pieces to be cleaner, faster or
more correct. The largest point is removing the old
arm_invalidate_caches() function and surrounding bootblock code to
initialize SCTLR and replace it with an all-assembly function that takes
care of cache and SCTLR initialization to bring the system to a known
state. It runs without stack and before coreboot makes any write
accesses to be as compatible as possible with whatever state the system
was left in by preceeding code. This also finally fixes the dreaded
icache bug that wasted hundreds of milliseconds during boot.
Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183890
(cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97)
nyan_big: apply cache-related changes from nyan
This applies the same changes from 07a3592 that were applied to nyan.
Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c
Reviewed-on: https://chromium-review.googlesource.com/184551
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea)
Squashed the followup patch for nyan_big into the original patch.
Change-Id: Id14aef7846355ea2da496e55da227b635aca409e
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
(cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch switches every last part of Coreboot on ARM over to Thumb
mode: libpayload, the internal libgcc, and assorted assembly files. In
combination with the respective depthcharge patch, this will switch to
Thumb mode right after the entry point of the bootblock and not switch
back to ARM until the final assembly stub that jumps to the kernel.
The required changes to make this work include some new headers and
Makefile flags to handle assembly files (using the unified syntax and
the same helper macros as Linux), modifying our custom-written libgcc
code for 64-bit division to support Thumb (removing some stale old files
that were never really used for clarity), and flipping the general
CFLAGS to Thumb (some more cleanup there as well while I'm at it).
BUG=None
TEST=Snow and Nyan still boot.
Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182212
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a)
Conflicts:
payloads/libpayload/include/arm/arch/asm.h
src/arch/arm/Makefile.inc
src/arch/arm/armv7/Makefile.inc
*** There is an issue with what to do with ramstage-S-ccopts, and
*** will need to be covered in additional ARM cleanup patches.
Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds another cache invalidation stub to the x86 arch to
make it usable in common code. This whole stuff should probably be
redesigned anyway but I just want to get it working and unblock my CL
for now... more cleanups coming later.
Change-Id: I2e8bdd8aa0e6723209384c24042f053f2e993fe6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182534
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit cafce5182a7a2a9ce17ad40d9d893a40ebd5aafd)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6919
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The memcpy/memset/memmove assembly implementations have been taken from
U-Boot, which originally got them from Linux. I turns out that they are
actually not that bad, but they could use an update. This patch pulls in
the current Linux upstream versions of those files, removing some old
U-Boot cruft such as checking whether the two pointers in a memcpy() are
equal (really now?) or side-stepping the R8 register because it was used
for special purposes. It also returns to the good old Linux
ENTRY/ENDPROC macros since we have them now anyway, and straightens out
the W() macro in preparation for unified thumb support.
Change-Id: I138af269b423bef0a237759ac29f1ee58ca206a0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182179
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 777127997bde5785b21d422d0b6eb04c4328b478)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6918
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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libgcc/macros.h contains some useful assembly macros that are common in
Linux kernel code and facilitate things such as unified ARM/THUMB
assembly. This patch moves it to a more general place where it can be
used by other code as well.
Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182178
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6917
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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This functionality is already available for ARM, so lets add it to x86 as
well. We'll want to be able to hook exceptions when running as a remote GDB
target.
Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6898
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This function returns the number of microseconds scaled from the number of raw
timer ticks. It accepts a base parameter which is subtracted from the current
time, which makes it easy to keep track of relative times.
Change-Id: I55f2f9e90c0e12cda430bbe88b044f12b0b563c8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179600
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4dd549e18d170dbf918c5b4b11bbe1f4e99b6695)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6897
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The xmalloc wrapper checks whether the malloc succeeded, and if not stops
execution and prints a message. xmalloc always returns a valid pointer. The
xzalloc wrapper does the same thing, but also zeroes the memory before
returning it.
Old-Change-Id: I00e7de04a5c368ab3603530b98bd3e3596e10632
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178001
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4029796d4f66601e33ae3038dbfc3299f56baf89)
libpayload: malloc: Fix xmalloc() for zero byte allocations
The C standard considers it legal to return a NULL pointer for zero
length memory allocations, and our malloc implementation does in fact
make use of that. xmalloc() and xzmalloc() should therefore not consider
this case a failure.
Also fixed a minor formatting issue.
Old-Change-Id: Ib9b75df9458ce2ba75fd0bc0af9814a3323298eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178725
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3033437e9d89c6072464860ea50ea27dcb76fe54)
Squashed 2 libpayload malloc related commits.
Change-Id: I682ef5f4aad58c93ae2be40e2edc1fd29e5d0438
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6890
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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If a programming error is detected, die can be used to print a message and
stop execution similar to failing an assert. There's also a "die_if" function
which is conditional.
die functions, like asserts, should be used to trap programming errors and not
when the hardware does something wrong. If all code was written perfectly, no
die function would ever be called. In other words, it would be appropriate to
use die if a function was called with a value that was out of bounds or if
malloc failed. It wouldn't be appropriate if an external device doesn't
respond.
In the future, the die family of functions might print a stack trace or show
other debugging info.
Old-Change-Id: I653fc8cb0b4e459522f1b86f7fac280836d57916
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178000
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 59df109d56a0f5346562de9b3124666a4443adf0)
libpayload: Fix the license in some files which were accidentally made GPL.
Some files were accidentally made GPL when they were added to libpayload. This
change changes them over to a BSD license to be in line with the intended
license of libpayload.
Old-Change-Id: Ia95ac4951b173dcb93cb489705680e7313df3c92
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/182202
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5f47600e50e82de226f2fa6ea81d4a3d1c56277b)
Squashed the initial patch for "die" functions and a later update to
the license header.
Change-Id: I3a62cd820e676f4458e61808733d81edd3d76e87
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6889
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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nyan: Clock setup.
Reviewed-on: https://chromium-review.googlesource.com/172106
(cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1)
tegra124: Call into the mainboard bootblock init if one exists.
Reviewed-on: https://chromium-review.googlesource.com/172581
(cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec)
nyan: Add a mainboard specific bootblock.
Reviewed-on: https://chromium-review.googlesource.com/172582
(cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69)
nyan: tegra124: Redestribute the clock code between the mainboard and soc.
Reviewed-on: https://chromium-review.googlesource.com/172583
(cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b)
nyan: Initialize the i2c pins and controllers.
Reviewed-on: https://chromium-review.googlesource.com/172584
(cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)
nyan: Initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/172585
(cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)
tegra124: add a chip.h and use it in NYAN
Reviewed-on: https://chromium-review.googlesource.com/172773
(cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f)
tegra: Reorder GPIO register accesses to avoid glitching
Reviewed-on: https://chromium-review.googlesource.com/172730
(cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5)
tegra: Turn GPIO wrappers into macros to make them easier to write
Reviewed-on: https://chromium-review.googlesource.com/172731
(cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c)
tegra: Change GPIO functions to allow variable arguments
Reviewed-on: https://chromium-review.googlesource.com/172916
(cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d)
tegra124: Implement starting up the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/172917
(cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3)
tegra: Simplify the I2C constants.
Reviewed-on: https://chromium-review.googlesource.com/172953
(cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76)
tegra124: Fix SPI base addresses
Reviewed-on: https://chromium-review.googlesource.com/173322
(cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357)
tegra124: Scrub the clock constants.
Reviewed-on: https://chromium-review.googlesource.com/172954
(cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4)
tegra124: add DMA support
Reviewed-on: https://chromium-review.googlesource.com/172951
(cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8)
tegra124: add basic SPI driver
Reviewed-on: https://chromium-review.googlesource.com/172952
(cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429)
tegra124: Add an assembly stub which is run first on the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/173541
(cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de)
nyan: tegra124: Set up dynamic cbmem.
Reviewed-on: https://chromium-review.googlesource.com/173542
(cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f)
tegra124: Add an soc.c which sets up the chip operations and memory resource.
Reviewed-on: https://chromium-review.googlesource.com/173543
(cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4)
tegra124: extend chip.h to include video settings
Reviewed-on: https://chromium-review.googlesource.com/173600
(cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29)
tegra124 and nyan: fill in the devicetree a bit more, add defines
Reviewed-on: https://chromium-review.googlesource.com/173684
(cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147)
tegra124: clean-ups for SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173599
(cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7)
tegra124: add a #define for DMA alignment size
Reviewed-on: https://chromium-review.googlesource.com/173638
(cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af)
tegra124: Add FIFO transmit functions to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173639
(cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7)
tegra124: clean-ups for DMA driver
Reviewed-on: https://chromium-review.googlesource.com/173598
(cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0)
tegra124: early display and display code.
Reviewed-on: https://chromium-review.googlesource.com/173622
(cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558)
tegra124: Move transfer size handling to spi_xfer()
Reviewed-on: https://chromium-review.googlesource.com/173680
(cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621)
tegra124: strict error detection and reporting for SPI
Reviewed-on: https://chromium-review.googlesource.com/173681
(cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010)
tegra124: add thread-friendly delays to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173648
(cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e)
Tegra124: Take the SPI1 controller out of reset and enable its clock.
Reviewed-on: https://chromium-review.googlesource.com/173787
(cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2)
tegra124: add two more clock setting values
Reviewed-on: https://chromium-review.googlesource.com/173772
(cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57)
nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC.
Reviewed-on: https://chromium-review.googlesource.com/173788
(cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8)
tegra124: Add some stub functions to the Tegra SPI driver.
Reviewed-on: https://chromium-review.googlesource.com/173789
(cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2)
tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS.
Reviewed-on: https://chromium-review.googlesource.com/173790
(cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084)
nyan: Implement the code which reads GPIOs for ChromeOS.
Reviewed-on: https://chromium-review.googlesource.com/173791
(cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3)
nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options.
Reviewed-on: https://chromium-review.googlesource.com/173792
(cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e)
Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.
Reviewed-on: https://chromium-review.googlesource.com/173793
(cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88)
tegra124: fix clear_fifo_status() in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173738
(cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f)
ARM: Include stdint.h in cpu.h.
Reviewed-on: https://chromium-review.googlesource.com/173774
(cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6)
tegra124: When setting up the main CPU, set its CPSR appropriately.
Reviewed-on: https://chromium-review.googlesource.com/173775
(cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead)
tegra124: fix wrong names in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/173955
(cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d)
tegra124: Fix up the PLLX divider table.
Reviewed-on: https://chromium-review.googlesource.com/173778
(cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17)
tegra124: clock: Get rid of cpcon and dccon.
Reviewed-on: https://chromium-review.googlesource.com/173779
(cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7)
Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
Reviewed-on: https://chromium-review.googlesource.com/173953
(cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355)
armv7: expose dcache_line_bytes() in cache API
Reviewed-on: https://chromium-review.googlesource.com/173975
(cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12)
libpayload: expose dcache_line_bytes() in ARM cache API
Reviewed-on: https://chromium-review.googlesource.com/174099
(cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9)
armv4: add a stub for dcache_line_bytes()
Reviewed-on: https://chromium-review.googlesource.com/173976
(cherry picked from commit 924f61ea895b9268c716791466637009bbac6469)
tegra124: Base early UART on CLK_M to enable debugging of PLL init code
Reviewed-on: https://chromium-review.googlesource.com/174339
(cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa)
tegra124: Add additional PLLs and redesign the divisor table
Reviewed-on: https://chromium-review.googlesource.com/174380
(cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384)
Squashed 49 commits for tegra124/nyan that included a lot of churn on
different pieces.
Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6869
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.
Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
ARM: Split out ARMv7 code and make it possible to have other arch versions.
We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.
The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.
Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)
Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.
Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
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This patch represents a major overhaul of the USB enumeration code in
order to make it cleaner and much more robust to weird or malicious
devices. The main improvement is that it correctly parses the USB
descriptors even if there are unknown descriptors interspersed within,
which is perfectly legal and in particular present on all SuperSpeed
devices (due to the SuperSpeed Endpoint Companion Descriptor).
In addition, it gets rid of the really whacky and special cased
get_descriptor() function, which would read every descriptor twice
whether it made sense or not. The new code makes the callers allocate
descriptor memory and only read stuff twice when it's really necessary
(i.e. the device and configuration descriptors).
Finally, it also moves some more responsibilities into the
controller-specific set_address() function in order to make sure things
are initialized at the same stage for all controllers. In the new model
it initializes the device entry (which zeroes the endpoint array), sets
up endpoint 0 (including MPS), sets the device address and finally
returns the whole usbdev_t structure with that address correctly set.
Note that this should make SuperSpeed devices work, but SuperSpeed hubs
are a wholly different story and would require a custom hub driver
(since the hub descriptor and port status formats are different for USB
3.0 ports, and the whole issue about the same hub showing up as two
different devices on two different ports might present additional
challenges). The stack currently just issues a warning and refuses to
initialize this part of the hub, which means that 3.0 devices connected
through a 3.0 hub may not work correctly.
Change-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170666
Reviewed-by: Kees Cook <keescook@chromium.org>
(cherry picked from commit ecec80e062f7efe32a9a17479dcf8cb678a4a98b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6780
Tested-by: build bot (Jenkins)
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This patch removes the confusing concept of a special "xhci_speed" with
a different numeric value from the usual speed used throughout the USB
core (except for the places directly interacting with the xHC, which are
explicitly marked). It also moves the MPS0 decoding function into the
core and moves some definitions around in preparation of later changes
that will make the stack SuperSpeed-ready. It makes both set_address
implementations share a constant for the specification-defined
SetAddress() recovery delay and removes pointless additional delays from
the non-XHCI version.
Change-Id: I422379d05d4a502b12dae183504e5231add5466a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170664
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit f160d4439c0d7cea1d2e6b97207935d61dcbb2f2)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This minor refactoring patch changes the signature of all limited cache
invalidation functions in coreboot and libpayload from unsigned long to
void * for the address argument, since that's really what you have in
95% of the cases and I think it's ugly to have casting boilerplate all
over the place.
Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167338
(cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6623
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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