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2014-08-10coreboot_tables: reduce redundant data structuresJulius Werner
There are three coreboot table tags that all define some kind of memory region, and each has their own homologous struct. I'm about to add a fourth so I'll just clean this up and turn it into a generic struct lb_range instead. Change-Id: Id148b2737d442e0636d2c05e74efa1fdf844a0d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167154 (cherry picked from commit 22d82ffa3f5500fbc1b785e343add25e61f4f194) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6456 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10libpayload: hexdump.c: Change type of length argument to size_tPaul Menzel
Representing a (non-negative) length with a signed integer is not optimal, so change its type to `size_t`. Change-Id: Ic0c2b7e081ba32d917409568ee53007d9ab7f8f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10serial: Separate the serial hardware init and the serial console init.Gabe Black
You might want to use the serial hardware for something other than a console, or you might want to intercede in the serial stream to wrap it in another protocol. This is what you'd do to send output to GDB while using it to debug the payload. Change-Id: I2218c0dbb988dacb64e5bdaf5d92138828eff8b6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179559 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit da9ab46d974745125fe7d8b29ce43336c3586cd5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6547 Tested-by: build bot (Jenkins)
2014-08-05libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.Gabe Black
When libpayload header files are included in the payload itself, it's possible that the payloads config settings will conflict with the ones in libpayload. It's also possible for the libpayload config settings to conflict with the payloads. To avoid that, the libpayload config settings have _LP_ (for libpayload) added to them. The symbols themselves as defined in the Config.in files are still the same, but the prefix added to them is now CONFIG_LP_ instead of just CONFIG_. Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65303 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6427 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-01armv7: add wrapper for DCCSW (data cache clean by set/way)David Hendricks
This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.Edward O'Callaghan
Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-30libpayload: Parse CBMEM ACPI GNVS pointerDuncan Laurie
Pull the ACPI GNVS pointer from CBMEM and expose it in the sysinfo structure for use by payloads. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I47c358f33c464a4a01080268fb553705218c940c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28libpayload: adjust max number of memrangesAaron Durbin
Rambi currently has more than 16 memory ranges. Because of this libpayload is silently dropping them and the full amount of memory is not being properly wiped. Correct this by bumping the number of ranges to 32. BUG=None BRANCH=None TEST=Built and booted rambi. Noted that the full amount of memory was being properly wiped. Change-Id: Ida456decf2498cb1547c0ceef23df446a975606b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175792 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4942 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-08libpayload: reintroduce optional PCI in XHCI driverPatrick Georgi
being a good citizen on the box, libpayload tries to return to EHCI mode on shutdown, so a non-XHCI capable USB driver after it (eg. in the OS) finds something to work with. Change-Id: Id227d646e08a258b841c644263112f0815dd486c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-21armv7: add wrappers to read/write L2ACTLRDavid Hendricks
This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21arm: libpayload: Include stdint.h in cache.hGabe Black
The cache.h header uses standard int types but doesn't include stdint.h itself. Change-Id: If470978164b0cd1f05c27c2c8eda365133cc47ff Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63190 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4387 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Libpayload: Add keyboard-disable function.Martin Roth
Add a function to disable and clear the keyboard controller. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I3e1f011c3436fee5ce10993c6c26a3c8597c6fca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63627 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4395 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-16libpayload: Add simple hexdump functionRonald G. Minnich
- prints hex and ascii - detects duplicate all zero lines Change-Id: I084b3072bc05725b23c5c3ca0dbf1533f164a08c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63660 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Author: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/4393 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-12libpayload: expose cbfs ram functionsAaron Durbin
The ram_media.c file is being compiled, however the global functions were not exposed through a header. Change-Id: I4588fbe320c29051566cef277bf4d20a83abf853 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56642 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4194 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12libpayload: armv7: Add cache control function to invalidate range.Hung-Te Lin
When dealing with DMA, we need a function to invalidate cache without corrupting contents on main memory (clean). Change-Id: I28e632ae57a7b7ed1accee74e76045b92f92a699 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61078 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05libpayload: Have similar cache api on ARM and x86Stefan Reinauer
So far this is used by the USB driver, and instead of having ifdefs all throughout that code, implement the same API on x86 and ARM. Change-Id: I8093ad818ad2e38a0901787aa8674faf591d580c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56105 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4320 Tested-by: build bot (Jenkins)
2013-12-05libpayload: sync ARMv7 arch/io.h with corebootStefan Reinauer
On ARMv7 we need to carefully add memory barriers to all memory read and write operations. This change brings libpayload in sync with what coreboot is doing. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c30b0f0d30531c5f9d99c2729246a86b8cec26 Reviewed-on: https://gerrit.chromium.org/gerrit/59294 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03Drop obsolete CONSOLE_LOGBUFStefan Reinauer
This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4256 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-26libpayload: Drop PowerPC architectureStefan Reinauer
This was never completed / working and we have the working ARMv7 port for an architecture template, so get rid of this dead code. Change-Id: Ic2c1267ee5546dd6e1b63220c263b2fa86c8ae33 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56065 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4235 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25libpayload: usb mass storage card hot plugAaron Durbin
Mass storage devices such as card readers show up as as USB devices. However the media not be inserted. In those situations the previous code would just fake a disk and call usbcreate_disk. This is inappropriate because it forms a 1:1 mapping of USB device to disk leading to the inability to remove the disk and/or handle "hot plug" card insertion and removals. To alleviate this issue introduce the notion of ready to the usbmsc structure. It tracks detached, not ready, and ready states. The polling routine is then used to track not ready to ready transitions thereby creating and removing disks appropriately. This handles the case of inserting and removing a card that shows up as a new disk. Booted recovery mode. Able to observe inerstion and removal of sdcard. Also able to insert valid USB flash drive to boot as well. Change-Id: I3eefbe537ec1b9c975744b8984b06c17ae236f40 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57948 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4226 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25libpayload: Add USB support for non-PCI controllersStefan Reinauer
Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 Reviewed-on: http://review.coreboot.org/4175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Make ssize_t an actual ssize_tStefan Reinauer
In the process of getting rid of compiler includes during in coreboot and libpayload, we defined size_t and ssize_t ourselves, using a GCC macro for size_t: __SIZE_TYPE__. Unfortunately, there is no __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make __SIZE_TYPE__ __SSIZE_TYPE__. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b Reviewed-on: https://gerrit.chromium.org/gerrit/49947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4156 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25armv7: import updated cache/MMU stuff from corebootDavid Hendricks
This imports the cache/MMU code from coreboot as of 1877cee. Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48288 Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4134 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-10libpayload: add memory clobber to ins{b,w,l}Gerd Hoffmann
Change-Id: I3c4b8a9eeb6c4b2bcc58ccff091b4c997b2da923 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4034 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-26libpayload: Add a few more PCI constantsStefan Tauner
flashrom has started to use revision IDs to distinguish AMD chipsets and fails (even more) to build with libpayload since then because PCI_REVISION_ID is undefined in libpayload's pci header. Change-Id: If7440a48c1005a4ba4fc09303f47cdfa9f408ad1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3884 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-08-15CBFS: Change the signature of cbfs_decompress.Gabe Black
Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-28libpayload: Add strerrorStefan Tauner
Change-Id: I33d45ad7d09473b8c6f5b7ee5fbadc0d184f9dcd Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3537 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-27libpayload: Add more integer limitsStefan Tauner
Change-Id: If0963237806804a2a9d7f622c33013321379a04d Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-27libpayload: Fix whitespace errorsStefan Tauner
Change-Id: Ibc36988745cbc7ede2a00da376b5dd295014ffb1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-13libpayload: usb: Add interval attribute to endpointsNico Huber
Read bInterval from endpoint descriptors and store it in our endpoint_t struct. The interval is encoded dependently on the device' speed and the endpoint's type. Therefore, it will be normalized to the binary logarithm of the number of microframes, i.e. t = 125us * 2^interval The interval attribute will be used in the xHCI driver. Change-Id: I65a8eda6145faf34666800789f0292e640a8141b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3449 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13libpayload: Redirect USB slave init through controller driverPatrick Georgi
xHCI requires special treatment of set_address since it determines the device number itself (instead of the driver, as with the other controllers). The controller also wants to validate a chosen device configuration and we need to setup additional structures for the device and the endpoints. Therefore, we add three functions to the hci_t structure, namely: set_address() finish_device_config() destroy_device() Current implementation for the Set Address request moved into generic_set_address() which is set_address() for the UHCI, OCHI and EHCI drivers. The latter two are only provided as hooks for the xHCI driver. The Set Configuration request is moved after endpoint enumeration. For all other controller drivers nothing changes, as there is no other device communication between the lines where the set_configuration() call moved. Change-Id: I6127627b9367ef573aa1a1525782bc1304ea350d Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3447 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13libpayload: Add enum for USB speedsNico Huber
These values are already used in this usb stack. Change-Id: If96f1dc2b67fbc13dfc4ae2d84e8f9945aa03163 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3448 Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-20Eliminate use of pointers in coreboot tableStefan Reinauer
Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3115 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-18libpayload: Don't sneak in compiler includesStefan Reinauer
The way we got to include the compiler includes was kind of whacky. Instead of mixing in potentially problematic headers, make libpayload self-contained by adding some missing header files. Also clean up conflicting definitions of size_t throughout the tree. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I0ad1194de1a00b7133c5477c00eb167d63a2ee85 Reviewed-on: https://gerrit.chromium.org/gerrit/47608 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3058 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-02libpayload: cbfs_core.h: Add missing third person s in »it need*s*«Paul Menzel
Introduced in »libpayload: New CBFS to support multiple firmware media sources.« (d01d0368) [1]. [1] http://review.coreboot.org/2191 Change-Id: I9feb9ab49825744cd00d6392a526f7af0ed053d1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2997 Reviewed-by: Nico Huber <nico.huber@secunet.com> Tested-by: build bot (Jenkins)
2013-03-30armv7: import updated cache/MMU stuff from corebootDavid Hendricks
This imports the newest cache and MMU code from coreboot. This time it's so new that it hasn't even been checked in to coreboot. However, this version at least allows DMA to work properly for the MSHC driver. So even if we rebase a few more times, this version is at least a step in the right direction. Note: This omits the stuff that sets up dcache policy since libpayload should not need to worry about that and it depends on cbmem stuff. Change-Id: Idd42b083e8019634aaaa44d5bf5b51db6c3912f5 Signed-off-by: David Hendricks <dhendrix@google.com> Reviewed-on: http://review.coreboot.org/2975 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-03-30armv7: import new cache maintenance API from corebootDavid Hendricks
This imports the new cache maintenance API from coreboot at commit bba8090. This is a BSD-licensed implementation which exposes cache maintenance opertaions necessary for payloads for things such as DMA transfers. Change-Id: I554676db89517bebc6edae4f7ab7e5882e6f986d Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2974 Tested-by: build bot (Jenkins)
2013-03-29libpayload: add x86 ROM variable MTRR supportAaron Durbin
On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the sysinfo structure. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-26libpayload: Fix type issuesStefan Reinauer
There were a number of type issues in libpayload that sneaked in with 903f8e0. - size_t and ssize_t were conflicting with gcc builtins - some stdint types were used in libpayload but not defined in our stdint.h With this patch it's possible to compile libpayload with the reference toolchain again. Change-Id: Idd5ccfdd9f3536b36bceca2d101e7405883b10bc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2903 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22libpayload: Add comments on virtual pointers in lib_sysinfoNico Huber
After another incident related to virtual pointers in lib_sysinfo (and resulting confusion), I decided to put some comments on the matter into the code. Remember, we decided to always use virtual pointers in lib_sysinfo, but it's not always obvious from the code, that they are. See also: 425973c libpayload: Always use virtual pointers in struct sysinfo_t 593f577 libpayload: Fix use of virtual pointers in sysinfo Change-Id: I886c3b1d182cba07f1aab1667e702e2868ad4b68 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/2878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-18libpayload: Make keycode constants available outside of curses.h.Gabe Black
And include the new, split out version in drivers/keyboard.c and drivers/usb/usbhid.c. Those files were including curses.h just for those definitions, but the include path was only fixed up to to point to the libpayload versions of those files if one of the variants of curses was compiled in. If neither was, gcc would fall back to the system version of that header which is wrong. Change-Id: I8c2ee0baf5f0702bd8c713c8dd4613a4bb269ce5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2762 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: add support for vboot_handoffAaron Durbin
The vboot_handoff structure needs to be parsed from the coreboot tables. Add a placeholder in sysinfo as well as the ability to parse the coreboot table entry concering the vboot_handoff structure. Built with unified boot loader and ebuild changes. Can find and use the VbInitParams for doing kernel selection. Change-Id: If40a863b4a445fa5f7814325add03355fd0ac647 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Turn the endian conversion macros into functions.Gabe Black
In their current macro form, any arguments that are expressions will be evaluated multiple times. That can cause problems if they have side effects, and might not even compile if the overall expression is ambiguous, for instance if you pass in foo++. Built with code that previously wouldn't compile because the macros expanded to ambiguous expressions. Change-Id: I378c04d7aff5b4ad40581930ce90e49ba7df1d3e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2719 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Generalize and redistribute timekeeping codeGabe Black
The timekeeping code in libpayload was dependent on rdtsc, and when it was split up by arch, that code was duplicated even though it was mostly the same. This change factors out actually reading the count from the timer and the speed of the timer and puts the definitions of ndelay, udelay, mdelay and delay into generic code. Then, in x86, the timer_hz and timer_get_raw_value functions which used to be in depthcharge were moved over to libpayload's arch/x86/timer.c. In ARM where there isn't a single, canonical timer, those functions are omitted with the intention that they'll be implemented by a specific timer driver chosen elsewhere. Change-Id: I9c919bed712ace941f417c1d58679d667b2d8269 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Add size_t and ssize_t types for ARM and x86Gabe Black
Some new TPM drivers in depthcharge require that type. I added it to arch/types.h which seemed appropriate, but I'm not sure that's exactly the right header to use, or in other words if you'd get that type from libpayload the same way you'd get it if you were building a standard Linux program. Also, I attempted to determine what underlying types gcc would use, and while I think I picked the right ones I'm not 100% certain of that either. Change-Id: Ic5c0b4173c8565ede3bfce8870976d596d69e51d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2669 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Add usb_generic_(create|remove) functions for unrecognized devicesGabe Black
It might be useful to provide a USB driver in the payload itself instead of in libpayload. For example there are multiple payloads being built and linked against the same libpayload, and they might not need or even want to have the same set of drivers installed. This change adds two new functions, usb_generic_create and usb_generic_remove, which behave like the usbdisk_create and usbdisk_remove functions which are defined for USB mass storage devices. If a USB device isn't recognized and claimed by one of the built in USB class drivers (currently hub, hid, and msc) and the create function is defined, then it will be called to give the payload a chance to use the device. Once it's removed, if usb_generic_remove is defined it will be called, effectively giving the payload notice. Built and booted depthcharge on Link. Built depthcharge for Daisy. Built a netbooting payload, called usb_poll() with those functions implemented, and verified that they were called and that the devices they were told about were reasonable and the same as what was reported by lsusb in the booted system. Change-Id: Ief7c0a513b60849fbf2986ef4ae5c9e7825fef16 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2666 Tested-by: build bot (Jenkins) Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Start using only internal and compiler headers.Ronald G. Minnich
When building other payloads with lpgcc the -nostdinc flag was injected into CFLAGS, but when building libpayload itself some headers were being used from the host system. This change puts -nostdinc into the Makefile and xcompile script, fixes up one include path in include/inttypes.h, adds the compiler provided include directory to the include search path, and deletes the two now redundant stdint.h files. BUG=None TEST=With this and other changes, built libpayload and depthcharge for Daisy, Link, and Fox. BRANCH=None Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-13libpayload: Add more parenthesis to the endian conversion macrosGabe Black
There weren't enough parenthesis in the macros so operations might only apply to the last part of an expression passed in as an argument. Change-Id: I5afb406f9409986e45bbbc598bcbd0dd8507ed35 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2665 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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