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2016-05-24arm64: Add stack dump to exception handlerJulius Werner
Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17libpayload: cbfs: Add cbfs_handle API for more fine-grained accessesJulius Werner
The libpayload CBFS APIs are pretty old and clunky, primarily because of the way the cbfs_media struct may or may not be passed in and may be initialized inside the API calls in a way that cannot be passed back out again. Due to this, the only real CBFS access function we have always reads a whole file with all metadata, and everything else has to build on top of that. This makes certain tasks like reading just a file attribute very inefficient on non-memory-mapped platforms (because you always have to map the whole file). This patch isn't going to fix the world, but will allow a bit more flexibility by bolting a new API on top which uses a struct cbfs_handle to represent a found but not yet read file. A cbfs_handle contains a copy of the cbfs_media needed to read the file, so it can be kept and passed around to read individual parts of it after the initial lookup. The existing (non-media) legacy API is retained for backwards compatibility, as is cbfs_file_get_contents() (which is most likely what more recent payloads would have used, and also a good convenience wrapper for the most simple use case), but they are now implemented on top of the new API. TEST=Booted Oak, made sure that firmware screens and software sync worked okay. Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09libpayload: ipq40xx: Introduce timer and uart driverVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload/arm64: Mark existing framebuffer as DMAablePatrick Georgi
If a framebuffer is already configured by coreboot, libpayload's MMU tables didn't mark its memory DMAable (unlike when libpayload set up its own framebuffer memory). BRANCH=none BUG=chrome-os-partner:52826 TEST=depthcharge's recovery screen is not corrupted anymore on kevin Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8 Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99 Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341092 Reviewed-on: https://review.coreboot.org/14685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: xhci: Set MPS based on speedVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Compiles and boots and detect USB storage BRANCH=none Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3 Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333311 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: Add nyan configPaul Kocialkowski
This adds a nyan libpayload config, that should fit all nyan devices. Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21libpayload: time: split time.h from libpayload.hStef van Os
Move time functions and prototypes from libpayload.h to time.h. In a similar manner to other c libary headers, this change makes porting existing applications to libpayload easier. Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648 Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com> Reviewed-on: https://review.coreboot.org/14437 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-18libpayload: disable EHCI & XHCI in defconfig-mipsMartin Roth
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h. barrier.h is present for x86, arm, and arm64, but not for mips. This is generating a build error after enabling USB by default on libpayload. I believe that this slipped through the buiders due to them not getting cleaned fully. It was caught in the coverity scan and when setting up a new build server. Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14391 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-04-16libpayload: Split off generic serial API from 8250 driverStefan Reinauer
There is a lot of generic code in the 8250 driver that should be available for non-8250 systems with serial ports as well. Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14371 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14libpayload: Enable USB support by defaultMarcel Meißner
Most people use USB keyboards. Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408 Signed-off-by: Marcel Meißner <mm-meissner@gmx.de> Reviewed-on: https://review.coreboot.org/7540 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-06libpayload/libc: Fix memset/sizeof usageJonathan Neuschäfer
Since r is a pointer, memset(r, 0, sizeof(r)) would only zero the first 4 (or 8) bytes of the newly allocated struct align_region_t. An alternative to this patch would be to use calloc, or introduce a new zalloc (zeroed allocation; a single-element calloc) and use that. Change-Id: Ic3e3487ce749eeebf6c4836e62b8a305ad766e7e Found-by: Coverity (ID 1291160) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14244 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-05libpayload: mmu: Initialize the base 4GiB as device memoryhuang lin
This allows to accommodate different platforms' default configurations, memory configuration is fine tuned later during boot process. BUG=chrome-os-partner:51537 BRANCH=none TEST=none yet, the full stack of patches boots fine on EVB Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97a9a71ade4df8a501043f9ae58463a3135e2a4f Original-Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332384 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-25libpayload: update junit.xml target, clean up outputMartin Roth
- Copy each config in configs/ to the junit_config, update each, in turn, and clean up when done. This avoids updating the saved config files and creating dirty files in git. - Use 'make olddefconfig' instead of 'yes "" | make oldconfig' - Update clean target to remove junit_config file - Update distclean target to remove junit.xml Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14164 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16libpayload: recreate config filesStefan Reinauer
Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-15libpayload: Move base address, stack and heap size to KconfigStefan Reinauer
This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Make comment into help textStefan Reinauer
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Fix ARM workaround codeStefan Reinauer
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10), so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised that this ever worked. Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Add comment about ARM64 exception stackStefan Reinauer
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Move MEMMAP_RAM_ONLY to generic optionsStefan Reinauer
MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Drop CONFIG_LP_CHROMEOSStefan Reinauer
This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Unify defconfigsStefan Reinauer
Bring defconfig and defconfig-tinycurses in sync, so that defconfig and defconfig-tinycurses only differ in the selection of the curses implementation. Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14069 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11codebase: Change makefile $(shell pwd) commands to $(CURDIR)Martin Roth
- Change the makefile command $(shell pwd) to $(CURDIR) to find the current directory without going out to the shell. Change-Id: I4890eba6129630acd2883b92de77308d39949443 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-22cbfs: Add LZ4 in-place decompression support for pre-RAM stagesJulius Werner
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-19libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSCAaron Durbin
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information exported in the coreboot tables as the cpu_khz frequency. That allows get_cpu_speed() not to be called which currently relies on the 8254 PIT. As certain x86 platforms allow that device to be optional or turned off for power saving reasons, allow a path where get_cpu_speed() is no longer called. Additionally, this approach also allows the libpayload to not duplicate logic that already exists in coreboot. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed in payload TSC frequency is honored instead of using get_cpu_speed(). Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13671 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-09libpayload: use 32bit access when accessing 4byte wide uart registersPatrick Georgi
This fixes serial on rk3288. Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13636 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-04libpayload: Add timer driver for armada38xRuilin Hao
Add timer driver for armada38x BUG=chrome-os-partner:47462 TEST=emerge-cyclone libpayload BRANCH=tot Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635 Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313343 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14cbgfx: add error code to cbgfx_initDaisuke Nojiri
cbgfx_init can fail for multiple reasons. These codes help debugging cbgfx_init. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315550 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-16libpayload: add archive.hDaisuke Nojiri
archive.h is a header file for the programs which need to parse an archive created by 'archive' tool. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311201 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/12734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.veyron: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.purin: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03libpayload: get cbfs offset & size for default media from lib_sysinfoDaisuke Nojiri
This change revives the path which was made inert by CL:308520. When media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer to a default media. Thus, get_cbfs_range does not set cbfs offset & size from lib_sysinfo. BUG=chrome-os-partner:47772 BRANCH=tot TEST=Tested on Jerry and Glados Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89 Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-28libpayload: Remove redundant 8250 MMIO32 UART driverAlexandru Gagniuc
The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-20libpayload: PDCurses: Remove trailing whitespaceStefan Reinauer
find . -type f |xargs perl -pi -e 's, *$,,' find . -type f |xargs perl -pi -e 's, *$,,' Change-Id: I62c2bc15b7c395a68b68422e701edf98b08e27c6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-13libpayload: udc/dwc2: Ignore setup packet in check for queue emptyFurquan Shaikh
during shutdown DWC2 UDC controller always requires an active packet to be present in EP0-OUT to ensure proper operation of control plane. Thus, during shutdown ignore EP0-OUT for queue empty check if only 1 packet is present. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. "fastboot reboot-bootloader" reboots device without timeout in udc shutdown. Change-Id: Iafe46c80f58c4cd57f8d58f060d805b603506bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4e7c27d849c0411aae58e60a24d8170a27ab8485 Original-Change-Id: Ifa493ce0e41964ee7ca8bb3a1f4bb8726fa11173 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311257 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12413 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-13libpayload: queue: Add a helper macro for checking singleton queueFurquan Shaikh
Check if the simple queue consists of only 1 element. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0 Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311256 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12412 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-11libpayload: Rename PDCurses-3.4 to PDCursesStefan Reinauer
Change-Id: If881ec130833c7e7e62caa3d31e350a531f5bc8e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11PDCurses: Don't hard code version numberStefan Reinauer
Don't hard code the PDCurses version number in every file added to the object list. Change-Id: Ic2e9230b7e3089c60dd7f442e3ea7baffb4aa400 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12397 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10libpayload/udc: dwc2: Add handler for add_stringsFurquan Shaikh
BUG=b:24676003 BRANCH=None TEST=Compiles successfully. fastboot devices shows serial number for shark. Change-Id: I61d6c168fa458d1f880bc566db997aa5d6398361 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 45b286b318281aea9a4b0362c9259d748b66fd28 Original-Change-Id: Ib9cc22de9daa6c5ec9cde1e62c6f5f768e946069 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310984 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10libpayload/udc: dwc2: Add timeout for shutdown operationFurquan Shaikh
BUG=b:24676003 BRANCH=None TEST=Verified that udc shutdown returns after the timeout. Change-Id: I5df598c4eddecbecb353343ef5a4e44eae4fc20b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 268913f21adea9969c9f88e3cb759341a60719f0 Original-Change-Id: I3ee059791d6e821f83f9ac41fd7c5385bd60e21e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310983 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12347 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-05libpayload: xhci: Add delay to get reset working more reliablyRajmohan Mani
Existing Intel xHCI controllers require a delay of 1 ms, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12325 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05libpayload: Avoid confusing usb debug output in dwc2 driverPatrick Georgi
enqueue_packet already runs start_ep_transfer, which enqueues the next job. It's pretty much guaranteed that the port will look busy. BUG=none BRANCH=none TEST=no spurious ep 0-0 busy messages Change-Id: I9cbfa7b51dd37564262295ddbcdd0755da40c05b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8997dbd78dc363334f4e22eaa61f25de1449ffba Original-Change-Id: I8a39713fc1d6f16b80284e0f21dc95685716a9b7 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308763 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: yunzhi li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/12259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05libpayload: Fix building dwc2 UDC driver with debug enabledPatrick Georgi
hexdump() now takes a pointer instead of an int-containing-an-address. BUG=none BRANCH=none TEST=building with USB_DEBUG works Change-Id: Idd0c43031a212c8f3b6489f533c488805d98d6a9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8660f6091bb124eeabe73302e8c7f1a8e46324f1 Original-Change-Id: I266efcb8b939d6da104ad05a3e79a78065c60beb Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308762 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: yunzhi li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/12258 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05libpayload: Allow non-default CBFS mediaPatrick Georgi
CBFS requests were always fulfilled using the CBFS specified in cbtables. That's a great policy when default requests are sought, but not so great when the user deliberately asked for something else. So check if they want default CBFS media information, otherwise ignore cbtables data. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I01b63049eebfba6f467808ac84ef77385840c204 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621c916ab14c0de4bae3dde09c05060c4f3c63c5 Original-Change-Id: Ia4a8848fd7db9d9a2bf9f5c226566fe3936ff543 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308520 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29libpayload: usbmsc: Add small delay during initialization to fix CZ60Julius Werner
We found that some SanDisk Cruizer Glide CZ60 sticks (confirmed on 16GB and 64GB versions) have a problem responding to our first GET_MAX_LUNS request right after they received their SET_CONFIGURATION. They will continually return a NAK until the host gives up (which is 2 user-noticable seconds for us). Adding a small delay of about 15us seems to be enough to fix the issue, but let's do 50 to be save. Confirmed with both MT8173 and Intel LynxPoint XHCI controllers. BRANCH=None BUG=chrome-os-partner:45473 TEST=No notable delay before detecting stick on Oak and Falco. Change-Id: Ib03944d6484de0ccecbb9922d22666f54c9d53dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 589f19a901275fb8b00de4595763a7d577bed524 Original-Change-Id: I95c79fe40d3ad79f37ce2eb586836e5de55be454 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308980 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29libpayload: Fix building dwc2 UDC driverPatrick Georgi
Change Ie54699162 changed a structure's name and field names and we didn't notice. Adapt. BUG=none BRANCH=none TEST=building with UDC_DWC2 works Change-Id: I592ebc29b2a08a23e6dbc9d2186807cbbbbca330 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3dda8ad5ffc36593d8b8fd6664a7f9b4816f0f93 Original-Change-Id: I4a065de0f4045a01bef1dc9fbb2e0578b5508518 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308791 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12228 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-28cbfs: read cbfs offset and size from sysinfoDaisuke Nojiri
This change allows libpayload to read cbfs offset and size from sysinfo. Legacy way of locating cbfs reagion is still supported in case sysinfo doesn't store the offset and the size. BUG=none BRANCH=master TEST=tested on samus and smaug Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296993 Original-Commit-Ready: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11557 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28cbgfx: Fix spelling of calculate_position()Jason A. Donenfeld
Change-Id: Ib0dc14b197091450596ad01a924539b0e69acd68 Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-on: http://review.coreboot.org/12216 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-27libpayload/libcbgfx: Add license headersPatrick Georgi
Change-Id: I09a9d9eef9d8fe45cdd4d68d29b8d662fe5956e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12164 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 05:50:16 +0000