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2016-10-17libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaultsJulius Werner
Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17libpayload: Replace majority of timer drivers with a generic oneJulius Werner
Currently every non-x86 platform supported by libpayload needs to provide its own timer driver. Most of the ones we have accumulated there look almost identical: For the frequency, return a preset constant. For the value, read a 32-bit register, possibly read another 32-bit register and shift+OR it with the previous one, then return that. Let's replace this with a single .c file that can easily handle all of those cases. Menuconfig convenience can still be maintained by providing several presets that select different defaults for the driver's configuration options (register address(es) and frequency). Removes an "enabled" check from Samsung MCT driver since coreboot always unconditionally enables that timer anyway. CQ-DEPEND=CL:344809 BRANCH=None BUG=None TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: a036af6 Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347749 Reviewed-on: https://review.coreboot.org/17023 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-09libpayload: mvmap2315: Introduce timer driverHakim Giydan
Testing: booted successfully. Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16692 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08libpayload: Fix strtok_rJeremy Compostella
This patch makes strtok_r: - handle the end of the string - handle string that contains only delimiters - do not set ptr outside of str Change-Id: I49925040d951dffb9c11425334674d8d498821f1 Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com> Reviewed-on: https://review.coreboot.org/16524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-08-27cbfs: Add "struct" file type and associated helpersJulius Werner
This patch adds functionality to compile a C data structure into a raw binary file, add it to CBFS and allow coreboot to load it at runtime. This is useful in all cases where we need to be able to have several larger data sets available in an image, but will only require a small subset of them at boot (a classic example would be DRAM parameters) or only require it in certain boot modes. This allows us to load less data from flash and increase boot speed compared to solutions that compile all data sets into a stage. Each structure has to be defined in a separate .c file which contains no functions and only a single global variable. The data type must be serialization safe (composed of only fixed-width types, paying attention to padding). It must be added to CBFS in a Makefile with the 'struct' file processor. Change-Id: Iab65c0b6ebea235089f741eaa8098743e54d6ccc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-13libpayload: head.S: Avoid clearing BSS (and heap) againJulius Werner
3 out of 4 architectures currently zero out the payload BSS in early assembly code, which is pointless since the code loading the payload has already done that (with a more efficient memset). ARM64 has never had any code like this and can run just fine without it. This also defeats the new optimization of moving the heap out of the BSS, since all three implementations assume that everything between _edata and _end is BSS. We should just take this out. Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-12libpayload: cbfs: Fix minor memory leak in some edge casesJulius Werner
cbfs_get_handle() allocates memory for a handle and doesn't free it if it errors out later, leaving the memory permanently leaked. Fix. Change-Id: Ide198105ce3ad6237672ff152b4490c768909564 Reported-by: Coverity Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16207 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08libpayload: lzma: Allocate scratchpad on the heapJulius Werner
Allocating a 15980-byte scratchpad on the stack when your default stack size is set to 16KB is really not a great idea. We're regularly overflowing into the end of our heap when using LZMA in libpayload, and just happen not to notice it because the heap rarely gets filled up all the way. Of course, since we always *have* a heap in libpayload, the much saner solution is to just use it directly to allocate the scratchpad rather than accidentally grow backwards into it anyway. Change-Id: Ibe4f02057a32bd156a126302178fa6fcab637d2c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16089 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08libpayload: arm64: Fix MMU range overlap checkJulius Werner
The ARM64 MMU code maintains a list of used ranges, to avoid mapping the DMA buffer over the coreboot tables and things like that. Unfortunately, the overlap with ranges in that list is checked with (start1 >= start2 && start1 <= end2) || (end1 >= start2 && end1 <= end2) which is not a full overlap check and misses the case where the second region is completely contained within the first. This patch replaces that code with a properly vetted primitive from Stack Overflow. BRANCH=none BUG=chrome-os-partner:54416 TEST=Observe how Kevin recovery screen now gets drawn at 10x the speed. Change-Id: I7e2706426762794e160d743bbfc40da1e26eee12 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02libpayload: split "Drivers" config section in KconfigAntonello Dettori
Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15914 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31libpayload: fix leak in libcbfsPatrick Georgi
stage wasn't freed on errors. Change-Id: I10d2f42f3e484955619addbef2898981f6f90a35 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347345 Reviewed-on: https://review.coreboot.org/15958 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31libpayload: Drop superfluous "continue"Patrick Georgi
Change-Id: I5a1d1ce8ba268b08d1275f392f0b9e602860c6ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260729 Reviewed-on: https://review.coreboot.org/15957 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02cbgfx: Use memset() for faster screen clearing if possibleJulius Werner
cbgfx currently makes a separate function call (recomputing some values) for every single pixel it draws. While we mostly don't care that much about display speed, this can become an issue if you're trying to paint the whole screen white on a lowly-clocked Cortex-A53. As a simple solution for these extreme cases, we can build a fast path into clear_screen() that just memset()s the whole framebuffer if the color and pixel format allow it. BUG=chrome-os-partner:54416 TEST=Screen drawing speed on Kevin visibly improves (from 2.5s to 3ms). Change-Id: I22f032afbb86b96fa5a0cbbdce8526a905c67b58 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15524 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21libpayload/pci: Correct MASK macro namesFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12libpayload: usb: xhci: Support rockchip xHCI controllerLiangfeng Wu
1. Make the xHCI driver to support xHCI controller v1.1 2. And a new function xhci_ring_doorbell(), it aims to add a memory barrier before ringing the doorbell, to ensure all TRB changes are written to memory. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB on Kevin rk3399 platform Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0c21e92 Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/346831 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15111 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-05-24arm64: Add stack dump to exception handlerJulius Werner
Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17libpayload: cbfs: Add cbfs_handle API for more fine-grained accessesJulius Werner
The libpayload CBFS APIs are pretty old and clunky, primarily because of the way the cbfs_media struct may or may not be passed in and may be initialized inside the API calls in a way that cannot be passed back out again. Due to this, the only real CBFS access function we have always reads a whole file with all metadata, and everything else has to build on top of that. This makes certain tasks like reading just a file attribute very inefficient on non-memory-mapped platforms (because you always have to map the whole file). This patch isn't going to fix the world, but will allow a bit more flexibility by bolting a new API on top which uses a struct cbfs_handle to represent a found but not yet read file. A cbfs_handle contains a copy of the cbfs_media needed to read the file, so it can be kept and passed around to read individual parts of it after the initial lookup. The existing (non-media) legacy API is retained for backwards compatibility, as is cbfs_file_get_contents() (which is most likely what more recent payloads would have used, and also a good convenience wrapper for the most simple use case), but they are now implemented on top of the new API. TEST=Booted Oak, made sure that firmware screens and software sync worked okay. Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09libpayload: ipq40xx: Introduce timer and uart driverVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload/arm64: Mark existing framebuffer as DMAablePatrick Georgi
If a framebuffer is already configured by coreboot, libpayload's MMU tables didn't mark its memory DMAable (unlike when libpayload set up its own framebuffer memory). BRANCH=none BUG=chrome-os-partner:52826 TEST=depthcharge's recovery screen is not corrupted anymore on kevin Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8 Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99 Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341092 Reviewed-on: https://review.coreboot.org/14685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: xhci: Set MPS based on speedVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Compiles and boots and detect USB storage BRANCH=none Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3 Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333311 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: Add nyan configPaul Kocialkowski
This adds a nyan libpayload config, that should fit all nyan devices. Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21libpayload: time: split time.h from libpayload.hStef van Os
Move time functions and prototypes from libpayload.h to time.h. In a similar manner to other c libary headers, this change makes porting existing applications to libpayload easier. Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648 Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com> Reviewed-on: https://review.coreboot.org/14437 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-18libpayload: disable EHCI & XHCI in defconfig-mipsMartin Roth
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h. barrier.h is present for x86, arm, and arm64, but not for mips. This is generating a build error after enabling USB by default on libpayload. I believe that this slipped through the buiders due to them not getting cleaned fully. It was caught in the coverity scan and when setting up a new build server. Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14391 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-04-16libpayload: Split off generic serial API from 8250 driverStefan Reinauer
There is a lot of generic code in the 8250 driver that should be available for non-8250 systems with serial ports as well. Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14371 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14libpayload: Enable USB support by defaultMarcel Meißner
Most people use USB keyboards. Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408 Signed-off-by: Marcel Meißner <mm-meissner@gmx.de> Reviewed-on: https://review.coreboot.org/7540 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-06libpayload/libc: Fix memset/sizeof usageJonathan Neuschäfer
Since r is a pointer, memset(r, 0, sizeof(r)) would only zero the first 4 (or 8) bytes of the newly allocated struct align_region_t. An alternative to this patch would be to use calloc, or introduce a new zalloc (zeroed allocation; a single-element calloc) and use that. Change-Id: Ic3e3487ce749eeebf6c4836e62b8a305ad766e7e Found-by: Coverity (ID 1291160) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14244 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-05libpayload: mmu: Initialize the base 4GiB as device memoryhuang lin
This allows to accommodate different platforms' default configurations, memory configuration is fine tuned later during boot process. BUG=chrome-os-partner:51537 BRANCH=none TEST=none yet, the full stack of patches boots fine on EVB Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97a9a71ade4df8a501043f9ae58463a3135e2a4f Original-Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332384 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-25libpayload: update junit.xml target, clean up outputMartin Roth
- Copy each config in configs/ to the junit_config, update each, in turn, and clean up when done. This avoids updating the saved config files and creating dirty files in git. - Use 'make olddefconfig' instead of 'yes "" | make oldconfig' - Update clean target to remove junit_config file - Update distclean target to remove junit.xml Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14164 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16libpayload: recreate config filesStefan Reinauer
Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-15libpayload: Move base address, stack and heap size to KconfigStefan Reinauer
This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Make comment into help textStefan Reinauer
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Fix ARM workaround codeStefan Reinauer
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10), so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised that this ever worked. Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Add comment about ARM64 exception stackStefan Reinauer
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Move MEMMAP_RAM_ONLY to generic optionsStefan Reinauer
MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Drop CONFIG_LP_CHROMEOSStefan Reinauer
This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15libpayload: Unify defconfigsStefan Reinauer
Bring defconfig and defconfig-tinycurses in sync, so that defconfig and defconfig-tinycurses only differ in the selection of the curses implementation. Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14069 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11codebase: Change makefile $(shell pwd) commands to $(CURDIR)Martin Roth
- Change the makefile command $(shell pwd) to $(CURDIR) to find the current directory without going out to the shell. Change-Id: I4890eba6129630acd2883b92de77308d39949443 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-22cbfs: Add LZ4 in-place decompression support for pre-RAM stagesJulius Werner
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-19libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSCAaron Durbin
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information exported in the coreboot tables as the cpu_khz frequency. That allows get_cpu_speed() not to be called which currently relies on the 8254 PIT. As certain x86 platforms allow that device to be optional or turned off for power saving reasons, allow a path where get_cpu_speed() is no longer called. Additionally, this approach also allows the libpayload to not duplicate logic that already exists in coreboot. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed in payload TSC frequency is honored instead of using get_cpu_speed(). Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13671 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-09libpayload: use 32bit access when accessing 4byte wide uart registersPatrick Georgi
This fixes serial on rk3288. Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13636 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-04libpayload: Add timer driver for armada38xRuilin Hao
Add timer driver for armada38x BUG=chrome-os-partner:47462 TEST=emerge-cyclone libpayload BRANCH=tot Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635 Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313343 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14cbgfx: add error code to cbgfx_initDaisuke Nojiri
cbgfx_init can fail for multiple reasons. These codes help debugging cbgfx_init. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315550 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-16libpayload: add archive.hDaisuke Nojiri
archive.h is a header file for the programs which need to parse an archive created by 'archive' tool. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311201 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/12734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.veyron: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.purin: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03libpayload: get cbfs offset & size for default media from lib_sysinfoDaisuke Nojiri
This change revives the path which was made inert by CL:308520. When media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer to a default media. Thus, get_cbfs_range does not set cbfs offset & size from lib_sysinfo. BUG=chrome-os-partner:47772 BRANCH=tot TEST=Tested on Jerry and Glados Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89 Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 23:07:35 +0000