summaryrefslogtreecommitdiff
path: root/payloads
AgeCommit message (Collapse)Author
2015-03-21libpayload arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc generates and handles exceptions properly Change-Id: If3ecab93be6d02942b52960ec97edc687bedf64b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bba2caae0bd436ba9e5215f5d8606ce8c4987c98 Original-Change-Id: I4abe8a0e426eab2532852179dbb32505353cd0a1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214609 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize exception stackFurquan Shaikh
Initialize exception stack to be able to handle exceptions properly BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc successfully generates and handles exceptions on ryu Change-Id: I19163fae080b9ac3297a7ffe404446e427bf9a1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99157687c5178c3b3eb79f5589343db1b2b4cc86 Original-Change-Id: I4dc83ff32c1665e22127bf0b1e6d4c6b45c07a4a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214608 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add console_init to enable console logsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles sucessfully and hello libpayload seen on screen Change-Id: If312e005e306f7f70138aa27d2ef5b39620ec91e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d6aa84d7255d33e085f12c609f32309521ff58e Original-Change-Id: I73f888a7b8aa0065c1ca0bf7857c445cc5678cdc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operationsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: mips: add SOC CPU frequencyIonela Voinescu
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: mips: correct platform IDIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8745 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: pistachio: fix timer implementationIonela Voinescu
timer_raw_value must return the number of CPU ticks, and not the time obtained by dividing the ticks by the CPU frequency. The CPU counter is increased at every 2 CPU clocks and therfore the number of ticks will be the counter value multiplied by 2. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; it works properly. BRANCH=none Change-Id: Iae62cb328e882f84822250bdf72146321ca9bbe0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ab25ce7dcaffb453ee774d870963a56444d46af Original-Change-Id: I74408950900463a2c054d5aebd3edb005a325adb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8744 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: mips: add memcmp to the MIPS string functionsIonela Voinescu
The default string functions work with multiple of 4 bytes (sizeof(unsinged long)); MIPS will use LW/SW instructions for these operations and if the source and destination addresses are not aligned it will trigger an exception. Therefore, this implementation does all data access operations per byte, because there is no guarantee that the provided strings are properly aligned. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected BRANCH=none Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241885 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu
Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: cbfs: Fix ram_media map() error return valueJulius Werner
The correct return value for errors on a cbfs_media->map() call is CBFS_MEDIA_INVALID_MAP_ADDRESS, not NULL. Not sure if that's the best choice (since 0xffffffff is probably a more likely valid address than 0 there), but that's what the upper layers expect right now. BRANCH=veyron BUG=None TEST=Press CTRL+L with an RW_LEGACY section filled with 0xff. Observe how cbfs_get_header() returns failure without doing a bunch of NULL pointer accesses first (not that those have any visible effect on Veyron, but that's another problem...) Change-Id: I3d012fc9af9da6e01159990a6bdd62c38fc22329 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a609e17bb9b0ef4d3a833f72fa4fbfd8e8cb0ab Original-Change-Id: I0793434116a8c568e19fe0dee24f13942fc50f25 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238991 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/8758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: Add RAM code to sysinfo_tDavid Hendricks
This adds CB_TAG_RAM_CODE and an entry to sysinfo_t. BUG=chrome-os-partner:31728 BRANCH=none TEST=Built and booted on pinky w/ depthcharge patch and saw that /proc/device-tree/firmware/coreboot/ram-code contains correct value Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f Original-Reviewed-on: https://chromium-review.googlesource.com/231132 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: Add support for parsing RAMOOPS range from corebootFurquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. ramoops console log verified after causing kernel to fault. Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6 Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228742 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: make wifi calibration table available through sysinfoVadim Bendebury
The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8753 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload arm64: Add function to get coreboot table ptrFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: If89e7a537e6f0321ef43641c924a8ef057f51147 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f39cdbf68b674ef9b65441038ec79548145a88d Original-Change-Id: Ie9904bf8abfa5ce1d87a586e5b08eb320793942f Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217821 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8790 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload ehci: Use 64-byte aligned data structures for periodic transfersJim Lin
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says "Frame List Link pointers always reference memory objects that are 32-byte aligned." jwerner@chromium.org suggests setting it to be 64-byte aligned for consistency with other EHCI queue structures. BUG=chrome-os-partner:31993 TEST=Tested on nyan platform. Before adding patch, USB keyboard behind an external hub is not working to switch between "Default Locale" and "English" (after pressing ESC+REFRESH+POWER on embedded keyboard and later Left/Right-Arrow key on USB keyboard). Change-Id: Ie6259f2df20ae2618c2074e831fad087f227091d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23fc02e6ba3b17be4eaf18810ec6fc0d9c0e0b9a Original-Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218403 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: EHCI: Fix transaction error for interrupt transferJim Lin
Data toggle should be running like 0, 1, 0, 1, ... In the failed case (where a low-speed USB keyboard or km232 device is installed), data toggle will be running as 0, 1, 0, 1, ..., 1, 1. Therefore causing Halted or Transaction Error bit to be set in qTD Status field. BUG=None BRANCH=None TEST=Tested on nyan_kitty platform, firmware-kitty-5771.61.B branch. Attached USB keyboard or km232 device to root-hub port (same side as SD card slot). Made sure no transaction error after doing interrupt transfer. Change-Id: I576f3c583dae4c279a6e0e8ffdfce5abe463277d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64b0428aaab869e20f6720669e953acf82ecb846 Original-Change-Id: Ic2c0f95cff2ae6e314967b0b82231a962255f1a7 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233857 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: provide basic 64bit division implementationVadim Bendebury
These functions are usually provided by gcc lib, which is not supposed to be included on embedded platforms. This patch adds a no thrills C implementation. Other than MIPS platforms are happy using the gcc library provided implementation, but in case of Chrome OS MIPS toolchain the libraries are compiled with the small GOT, such that the entire data segment does not fit. With this implementation mips, arm and x86 targets build fine. BRANCH=none BUG=chrome-os-partner:31438 TEST=checked the logic by incorporating this code into a C file and running a loop continuously comparing random inputs' division and left and right shift results. The test ran for extended periods of time without failure. Change-Id: I468acd2fdbcdd493a76758a394e79cad35f9535a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2cc5f8668dd2609408af8da5a74c5a3d063fc0d3 Original-Change-Id: Ib46616d7eb0b2b497199270057514f730bb1cb0b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplicationVadim Bendebury
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: cros: include mac addresses in coreboot tableVadim Bendebury
Pass MAC addresses found in coreboot table into lib_sysinfo. BUG=chrome-os-partner:32152 TEST=with all changes in place MAC addresses are properly inserted into the kernel device tree. Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78 Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload: Consolidate coreboot table parsingVadim Bendebury
There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Add board id parsingVadim Bendebury
Make board ID value supplied in the coreboot table available to the bootloader on all three architectures. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210430 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Do not include gcclib for mips targetsVadim Bendebury
As opposed to other architectures, on MIPS gcc toolchain provided gcclib is not always adequate, for instance when the library does not account for the case when data segment is too large to fit into the 64K GOT. Let's make sure the library is not included when building for MIPS targets. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of patches applied the FPGA board boots all the way to verifying and loading the kernel from the USB stick. Change-Id: I710d3c49bdc57877152cf28d5bd8cb4fa4d0b9ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8d7d84c81af7e3eee1c8f3304c15069e8701cde Original-Change-Id: I1a26b9e575a20101329359b80dffc236ef7f9e9f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload console: Add check for already existing driverFurquan Shaikh
Add support to check if the driver for console_out or console_in is already present in the list. If console_init is called twice, then the driver might get added twice leading to a loop. BUG=None BRANCH=None TEST=With console_init in libpayload and depthcharge both, there are no console loops seen anymore Change-Id: I9103230dfe88added28c51bff33ea4fa1ab034c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6931236ba2cfa71849973fe41cc340b7d70656ad Original-Change-Id: If9a927318b850ec59619d92b1da4dddd0aa09cd1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214072 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: UTF-16LE to ASCII conversionDan Ehrenberg
This patch adds a simple function to convert a string in UTF-16LE to ASCII. TEST=Ran against a string found in a GPT with the intended outcome BRANCH=none BUG=none Change-Id: I94ec0a32f5712259d3d0caec2233c992330228e3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1104db8328a197c7ccf6959a238277f416a2113a Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Change-Id: I50ca5bfdfbef9e084321b2beb1b8d4194ca5af9c Original-Reviewed-on: https://chromium-review.googlesource.com/231456 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: special case large memalign() requestsAaron Durbin
For memalign() requests the current allocator keeps metadata about each chunk of aligned memory that copmrises the size requested. For large allocations relative to the alignment this can cause significant metadata overhead. Instead, consider all memalign() requests whose size meets or exceeds 1KiB or alignment that meets or exceeds 1KiB large requests. These requests are handled specially to only allocate the amount of memory required for the size and alignment constraints by not allocating any metadata as the whole region would be consumed by the request. BUG=None BRANCH=None TEST=Built and tested various scenarios. Noted the ability to free() and properly coalesce the heap as expected. Change-Id: Ia9cf5529ca859e490617af296cffd2705c2c6fd8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4e32fc57626dac6194c9fd0141df680b4a5417e8 Original-Change-Id: Icdf022831b733e3bb84a2d2f3b499f4e25d89128 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242456 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload/usb: wait a millisecond to work around device bugsPatrick Georgi
Some USB sticks seem to send a NAK at a place where they mustn't by spec, leading to a controller side error condition. To avoid it, wait a millisecond which is enough to get past the NAK condition. That delay only happens on device discovery so it won't affect boot time by more than 1ms per device. BUG=chromium:414959 BRANCH=none TEST=depthcharge recognizes a Lexar 16GB USB stick after applying this change. Change-Id: I0e385702a5259b16fda0a253fc121d8f66e6705c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10bbfda8395af009e7f910cc503f50c2ad969ae8 Original-Change-Id: I6dd5ca34e9f3767003ccb0ca9daaf16116f4a2df Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228791 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-on: http://review.coreboot.org/8735 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-19libpayload EHCI: Add memory barrier to EHCI driverFurquan Shaikh
EHCI driver accesses mmio space using regular struct pointers. In order to avoid any CPU re-ordering, memory barrier is required in async_set_schedule, especially for arm64. Without the memory barrier, there seems to be re-ordering taking place which leads to USB errors with some flash drives as well as transfer errors in netboot. BUG=chrome-os-partner:31533 BRANCH=None TEST=With the memory barrier introduced, netboot for ryu completes transfer without any error and finishes within 6-7 seconds. Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213917 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload: Add support for memory barriersFurquan Shaikh
Add support for memory barriers in arch {arm,arm64,x86}. This is required to force strict CPU ordering. Definitions are based on FREEBSD atomic.h definitions. BUG=chrome-os-partner:31533 BRANCH=None TEST=Memory barriers tested with ehci driver on arm64 Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552 Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213916 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8731 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload: add xmemalign()Aaron Durbin
Similarly to xzalloc() and xmalloc() provide an xmemalign() function to do the approriate assertions on allocation failure. BUG=None BRANCH=None TEST=Built and booted using xmemalign(). Change-Id: I59579d9ee973af3bb34037b7df5b1024b60e348d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3001822656024dbfc34d6b849a0245274b8c0f46 Original-Change-Id: Ie307d4c9c1882bba25745afe38455f2682303e37 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242455 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8728 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload: Add OpenBSD queue implementationPatrick Georgi
Add OpenBSD's header-only implementation of some basic data structures, imported from src/sys/sys/queue.h, revision 1.38 (all whitespace errors kept verbatim) Unlike home-grown solutions they likely handle all corner cases correctly from the start and unlike Linux's solution it's properly documented (see OpenBSD's LIST_INIT(3)) and also BSD-l. BRANCH=none BUG=none TEST=none Change-Id: I89ae4df0c73662c355537283e7559af03a8b99a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f89e0316e6d68158c689bed4b1bdfe168c1449a Original-Change-Id: Ie08a567851a2f07cbd2ac80ba31d8bca9844937d Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8727 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13libpayload: ipq808x: stale interrupt shall not be cleared unconditionallyYogesh Lal
The serial driver hangs in cases when FIFO has more than single word to be processed. Easiest way to reproduce is to paste a string of greater than 4 characters in cli. Clearing the RXSTALE interrupt without draining all the characters from FIFO leads to the issue as the driver is dependent on msm_boot_uart_dm_read function to reinitialize for next transfer. Logically the driver is organized in such a manner that next transfer never gets initiated till rx_data_read < total_rx_data. Clearing the RXSTALE without consideration of total number of characters (or words) unprocessed makes the msm_boot_uart_dm_read to return on the first if conditional. Thus the driver is stuck forever. A quick fix is to avoid clearing the stale interrupt. Reset is handled whenever a new transfer is initialized in msm_boot_uart_dm_init_rx_transfer. BUG=chrome-os-partner:29542 TEST=manual -Paste a string greater than 4 characters in cli. Original-Change-Id: I016afb01a77cd14764f0176f6bf144fb29796c2f Original-Signed-off-by: Yogesh Lal <ylal@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209512 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 61528884ad2c0a8e146054bbfeb01a3bc73b9692) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I936af5daa52a25f62133bdf9fb44f0b68cf34e88 Reviewed-on: http://review.coreboot.org/8667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-04libpayload: Don't try to free individual xhci device slotsPatrick Georgi
`di` points to a single item in xhci->dev[], which is malloc'd collectively. Trying to free() leads to pain. Change-Id: Ibd99eda905d43cbf2d2c111dfd0186ed6b119329 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8515 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-25nvramcui: don't init curses too earlyLubomir Rintel
Init curses as late as possible and tear them down early. There are possible error outs after that and they don't look nice with curses initialized. Change-Id: I9128ae8eee25940716b8d223cc7ec6c0abb6838e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: http://review.coreboot.org/8528 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25nvramcui: fix a buffer overflowLubomir Rintel
Missing parentheses around addition. ==22611== Invalid write of size 8 ==22611== at 0x401B26: main (nvramcui.c:146) ==22611== Address 0x5a67c40 is 32 bytes inside a block of size 33 alloc'd ==22611== at 0x4C2BC0F: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==22611== by 0x401AA9: main (nvramcui.c:137) Change-Id: I9fd6a619dd03ebaaa066bca8fa5838e76374c984 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: http://review.coreboot.org/8527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25nvramcui: don't wait for the first key update to render the formLubomir Rintel
Flush out the initial screen window and render the form before the first keypress. It looks overly weird otherwise and is very likely unintended. Change-Id: I8700e36e608f2ba115359070f75b7dc9f230291e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: http://review.coreboot.org/8526 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25nvramcui: drop unused variableLubomir Rintel
nvramcui.c: In function ‘main’: nvramcui.c:68:8: warning: unused variable ‘cur’ [-Wunused-variable] ITEM *cur; ^ Change-Id: I5c692fc2e6da460cd7c6f7978378c92587d829d2 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: http://review.coreboot.org/8525 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-23libpayload: Improve sanity checking in UHCI driverPatrick Georgi
Test for devno != -1 before trying to access array[devno] (which may be array[-1]). Change-Id: Ia69cc7eba0335f02bb0efec003a320a3c0646acb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8509 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-23libpayload: avoid use-after-free in OHCI driverPatrick Georgi
Change-Id: I89294c22c57564262e53e36c5ae9ac6eb0ed934a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8510 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-12Use ALIGN_UP instead of manual alignmentPatrick Georgi
BUG=none BRANCH=none TEST=none Change-Id: I56f357db6d37120772a03a1f7f84ce2a5b5620e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/241855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8396 Tested-by: build bot (Jenkins)
2015-01-12libpayload: Let GDB stub read/write memory with aligned MMIO wordsJulius Werner
Looks like we got our first SoC that actually insists on using word-sized accesses for its MMIO registers with the Rk3288. This patch changes the GDB command handler for reading and writing memory to always perform word-sized accesses. This isn't really perfect since the remote GDB interface is just not really meant to interact with MMIO (e.g. you shouldn't use this on something with read side effects), but for most of our purposes it should be good enough. BUG=chrome-os-partner:18390 TEST=Remote GDB works on Veyron even when writing MMIO registers. Original-Change-Id: I2ae52636593499f70701582811f1b692c1ea8fcc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208554 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 028940934e6b45a02122b61bb859588bf8671938) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4185a6efe9a5211525781acd0a167b821e854211 Reviewed-on: http://review.coreboot.org/8130 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: Expand setbits_le32() and fix readl() const-nessJulius Werner
setbits_le32() is not really arch-specific... the arch-specific part of accessing memory is wrapped by readl() and writel(), and the endianness can be accounted for with the right macros. Generalize the definitions, add a be32 version and move them to endian.h so that all platforms can use them. Also include endian.h from libpayload.h so we won't update any payload's old use of the macros (endianness is something useful enough to always have avalable anyway, and shouldn't clash with other things). This also fixes a bug where these macros would only be available if libpayload-config.h had been independently included before. Also fix a bug with readl() macros on all archs where they refused to work on const pointers (which they should). CQ-DEPEND=CL:208712 BUG=None TEST=Stuff still compiles. Built and booted on Storm. Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208713 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8 Reviewed-on: http://review.coreboot.org/8129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: improve us timer accuracyVadim Bendebury
In cases where timer clock frequency is not an integer number of megahertz, the calculations in timer_us() lack accuracy. This patch modifies calculations to reduce the error. The maximum interval this calculation would support decreases, but it still is in excess of 1844674 seconds for a timer clocked by 10 MHz, which is more than enough. BUG=none TEST=manual . verified timer accuracy using a depthcharge CLI command Original-Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207358 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e1abf87d438de1a04714482d5b610671e8cc0663) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia892726187ab040dd235f493c92856c15951cc06 Reviewed-on: http://review.coreboot.org/8128 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-12libpayload: Add Rock Chip drivershuang lin
Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-09libpayload: Reorder default memcpy, speed up memset and memcmpJulius Werner
The current default memcpy first copies single bytes to align the amount, then copies the rest as full words. In practice, the start of a buffer is much more likely to be word-aligned then the end, and aligned word access are usually more efficient. This patch reorders those accesses to first copy as many full words as possible and then finish the rest with byte accesses to optimize this common case. This fixes a data abort when using USB on ARM without CONFIG_GPL. Due to some limitations of how DMA memory is set up in coreboot on ARM, it currently does not support unaligned accesses. (This could be fixed with a more complicated patch, but it's usually not an issue... unless, of course, your memcpy happens to be braindead). Also add word-aligned accesses to memset and memcmp while I'm at it, and make memcmp's return value standard's compliant. BUG=chrome-os-partner:24957 TEST=Manual Original-Change-Id: I2a7bcb35626a05a9a43fcfd99eb958b485d7622a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203547 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 05a64d2e107e1675cc3442e6dabe14a341e55673) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0030ca8a203c97587b0da31a0a5e9e11b0be050f Reviewed-on: http://review.coreboot.org/8126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add gdb stub for arm64Furquan Shaikh
Add stub implementation for gdb arm64 support. Currently all functions are kept empty to enable proper compilation of depthcharge and libpayload. As we get more clear about context management and stuff, we can add details for gdb as well. BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0a8729671ab0764d424c0e3d50af86433d05b1e8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204877 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d24e5c26b56a9882b3450b1e4988b56c3d73efd1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9b7d3d7060dd827ef4a46865e0f9a2b4e063d07d Reviewed-on: http://review.coreboot.org/8125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add selfboot.c required by depthchargeFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I2569cadf2d34f7211892f100ba715486d824b921 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204611 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit dd9e06e41da043a48b469a011c010a10a1a3b25a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I37fbc8cfea0870e7167ffa47dd63fc548e18c82e Reviewed-on: http://review.coreboot.org/8124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Fix baseaddr access in serial/tegra.cFurquan Shaikh
Fix baseaddr typecast to allow use in 32- and 64-bit systems BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie5ded744d75a0ae4d1428d04ff2478bdfe54d146 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204424 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b56814fe5fc7d3a2fdfb324d4baafb27a9d3ffd6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icedc1c819e39b92a0dd92e98f848e15b3039dfbe Reviewed-on: http://review.coreboot.org/8123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Correct function names for tlb invalidationFurquan Shaikh
Correct function names to make them consistent with depthcharge calling convention BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0fd8f7f929c3fe268710362d1fc19f9e15c4a23b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 36008e728b840d85bb98225c7bb1420b993181de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4b446da8f2c273385ee885c4870966e18ba2a7a6 Reviewed-on: http://review.coreboot.org/8122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload arm64: Add dummy_media fileFurquan Shaikh
This is required for proper compilation of libpayload and depthcharge BUG=None BRANCH=None TEST=libpayload compiles successfully for rush Original-Change-Id: I305b58b978fd335e20abd7664c3ee2a6c1ea8384 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204422 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit eef115c2371c6f7259bf808e0448f24a5b3491ab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icd6a5b8a0bdb125de4913fc82be8cb2a5aef5dc9 Reviewed-on: http://review.coreboot.org/8120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Add remote GDB supportJulius Werner
This patch adds the ability to attach a GDB host through the UART to a running payload. Libpayload implements a small stub that can parse and respond to the GDB remote protocol and provide the required primitives (reading/writing registers/memory, etc.) to allow GDB to control execution. The goal of this implementation is to be as small and uninvasive as possible. It implements only the minimum amount of primitives required, and relies on GDB's impressive workaround capabilities (such as emulating breakpoints by temporarily replacing instructions) for the more complicated features. This way, a relatively tiny amount of code on the firmware side opens a vast range of capabilities to the user, not just in debugging but also in remote-controlling the firmware to change its behavior (e.g. through GDBs ability to modify variables and call functions). By default, a system with the REMOTEGDB Kconfig will only trap into GDB when executing halt() (including the calls from die_if(), assert(), and exception handlers). In addition, payloads can manually call gdb_enter() if desired. It will print a final "Ready for GDB connection." on the serial, detach the normal serial output driver and wait for the commands that GDB starts sending on attach. Based on original implementation by Gabe Black <gabeblack@chromium.org>. BUG=chrome-os-partner:18390 TEST=Boot a GDB enabled image in recovery mode (or get it to hit a halt()), close your terminal, execute '<toolchain>-gdb --symbols /build/<board>/firmware/depthcharge_gdb/depthcharge.elf --directory ~/trunk/src/third_party/coreboot/payloads/libpayload --directory ~/trunk/src/platform/depthcharge --directory ~/trunk/src/platform/vboot_reference --ex "target remote <cpu_uart_pty>"' and behold the magic. (You can also SIGSTOP your terminal's parent shell and the terminal itself, and SIGCONT them in reverse order after GDB exits. More convenient wrapper tools to do all this automatically coming soon.) Original-Change-Id: Ib440d1804126cdfdac4a8801f5015b4487e25269 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202563 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 9c4a642c7be2faf122fef39bdfaddd64aec68b77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9238b4eb19d3ab2c98e4e1c5946cd7d252ca3c3b Reviewed-on: http://review.coreboot.org/8119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 09:16:59 +0000