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2020-10-22drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph
SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-20libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()Felix Singer
Clean up ahci_initialize() by using pci_dev struct. Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/storage/ahci: Use pacc pointer to read device classFelix Singer
The PCI bus gets already scanned while gathering system information. Therefore, use the pacc pointer from sysinfo_t to read the device class of PCI devices instead of rescanning the bus. Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/arch/x86: Introduce pacc pointer in sysinfo_t structFelix Singer
Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20payloads/coreinfo: Rename pci_scan_bus()Felix Singer
Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19libpayload/storage: Enable STORAGE_64BIT_LBAFelix Singer
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB capacity. Therefore, enable the 64-bit support. Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19libpayload/storage: Enable all AHCI controllers by defaultFelix Singer
Since the list of tested controllers is not actively maintained, enable all AHCI controllers by default. Also, improve the readability of its help text by adding a comma to it. Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-17libpayload/libpci: Introduce device class attribute in pci_devFelix Singer
The device class is read at different places and it is read from the hardware directly. Therefore, and in preparation to CB:46416, introduce the device class attribute in the pci_dev struct. With this, there is only one interaction with the hardware and it's also more user friendly. Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46347 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17libpayload/libpci: Clean up pci_alloc()Felix Singer
Clean up pci_alloc() and return pointer to allocated memory directly. Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-16libpayload/x86: Add some more CPUID helpersNico Huber
Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-15lib and libpayload: Add popcnt functionsAngel Pons
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers. Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14lib and libpayload: add 64-bit versions of clz, __ffs and log2Tim Wawrzynczak
Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`, and `log2_64`. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30libpayload: use PRIu64 type to print u64Jeremy Compostella
The appropriate way to print a u64 variable regardless of the current architecture is to use the PRI*64 macros. libpayload is mostly used in 32 bits but when ported to other projects and compiled in 64 bits it breaks the compilation. Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7633 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-09-27libpayload: Fix file permissionsKyösti Mälkki
Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26payloads/external: add support for BOOTBOOT payloadZoltan Baldaszti
BOOTBOOT is a multi-platform, architecture agnostic boot protocol. The protocol describes how to boot an ELF64 or PE32+ executable inside an initial ram disk image into clean 64 bit mode. This version uses libpayload to do that. Depending on the lib's configuration, initrd can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT partition or a file on a FAT formatted ESP partition. For more information see https://gitlab.com/bztsrc/bootboot Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0 Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21treewide/Kconfig: Drop unneeded empty linesElyes HAOUAS
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21payloads: Drop unneeded empty linesElyes HAOUAS
Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-19libpayload: free: Separate NULL check out for clarityHsuan Ting Chen
Separate the validity check of calling free(NULL) for clarity. BUG=b:168441735 TEST=emerge-puff libpayload Change-Id: I0dc355553410bbe59e658945fb40c05f5f709380 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18libpayload: cbgfx: Fix 'equals' counter for Lanczos resamplingYu-Ping Wu
The current initialization of the 'equals' counter is incorrect, so that when 'equals >= SSZ * SSZ', the pixels in the sample array might not be all the same, leading to a wrong pixel value being set in the framebuffer. The 'equals' counter stores the number of latest pixels that were exactly equal. Within the for loop of 'ox', the sample array is updated in a column-based order, and the 'equals' counter is updated accordingly. However, the 'equals' counter is initialized in a row-based order, which causes it to be set too large than it should be. Consider the example where sample[sx][sy] are initially: [X X X A A A] // sy = 0 [X X X B B B] [X X X B B B] [X X X B B B] [X X X B B B] [X X X B B B] // sy = SSZ Then, the correct implementation will initialize 'equals' to be 15, with last_equal being B. Suppose all of the remaining pixels are B. Then, at the end of the 'while (fpfloor(ixfp) > ix)' loop when ix = 4, or equivalently after 4 more columns of sample are updated, 'equals' will be 15 + 6 * 4 = 39, which is greater than SSZ * SSZ = 36, but we can see there are still 2 A's in the sample: [B B B B A A] [B B B B B B] [B B B B B B] [B B B B B B] [B B B B B B] [B B B B B B] Therefore, we must also initialize the 'equals' counter in a column-based order. BUG=b:167739127 TEST=emerge-puff libpayload TEST=Character 'k' is rendered correctly on puff BRANCH=zork Change-Id: Ibc91ad1af85adcf093eff40797cd54f32f57111d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-14coreinfo: Use SPDX license identifiersJacob Garber
- Remove copyright notices and add authors to AUTHORS - Use SPDX license identifiers for all files - Add coreinfo to the license header lint Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-13libpayload: malloc: Fix realloc for overlapping buffersYu-Ping Wu
The current realloc() works by freeing the origin buffer, allocating a new one, and copying the data over. It's true that free() won't touch the actual memory. However, the alloc() following it will potentially modify the memory that belongs to the old buffer in order to create a new free block (right after the newly allocated block). This causes 8 bytes (HDRSIZE) to be overwritten before being copied to the new buffer. To fix the problem, we must create the header of the new free block after the data is copied. In this patch, the content of alloc() is split into two functions: 1. find_free_block(): Find a free block with large enough size, without touching the memory 2. use_block(): Update the header of the newly allocated block, and create the header of the new free block right after it Then, inside realloc(), call memmove() call right after find_free_block() while before use_block(). BUG=b:165439970 TEST=emerge-puff libpayload TEST=Puff boots TEST=Verified realloc() correctly copied data when buffers overlapped Change-Id: I9418320a26820909144890300ddfb09ec2570f43 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-04libpayload/xhci: Fix Slot State field width definitionCaveh Jalali
According to the xHCI spec, the Slot State field in the Slot Context Data Structure is 5 bits wide. So, fix the code to match. ref. xHCI spec 1.2 section 6.2.2, Figure 6-2: Slot Context Data Structure BUG=none TEST=xHCI compiles Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45023 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31xhci: Do not set the CRCR_CS bitCaveh Jalali
We do not need to set the CS (Command Stop) bit in the Command Ring Control Register. CS is implied by CA (Command Abort). I'm not sure if there is a defined execution order for these command bits, so it's safer to only use the CA bit as it includes the CS function. Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24. BUG=b:160354585,b:157123390 TEST=able to boot into recovery using USB stick on servo v2 on volteer as well as HooToo 8-1 hub Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-31xhci: Fix Abort command event handlingCaveh Jalali
This fixes issues with how we handle events generated by the xHCI "command abort" command. first, depending on the state of the xHCI controller, the COMMAND_ABORTED may not be generated. If the controller was between commands, only the COMMAND_RING_STOPPED event will be generated. Second, do not adjust the command ring "cur" pointer as that just confuses the controller. BUG=b:160354585,b:157123390 TEST=able to boot into recovery using USB stick on servo v2 on volteer as well as HooToo 8-1 hub Change-Id: I055df680d1797f35d9730e2bfdb4119925657168 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-28libpayload: cbgfx: Support buffered I/OHung-Te Lin
For payloads with UI based on CBGFX, they usually start by calling clear_canvas or clear_screen and then draw the UI elements. However, that makes the screen flicker. A typical solution is to identify and minimize the area to redraw. However for payloads with complicated UI and do not care about latency, an alternative is to enable buffered I/O. The new enable_graphics_buffer() will redirect all graphics I/O into an invisible working buffer. To flush (redraw) the buffer to the real screen, call flush_graphics_buffer(). To stop buffering, call disable_graphics_buffer(). BUG=None TEST=Add the enable, flush and disable calls to payload 'depthcharge', built a firmware and boots into Chrome OS recover UI. No more flickering. The average rendering time on x86 platform is 1.2ms. Change-Id: Id60a2824fd9e164feae16b92b68b003beabea8d3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44654 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24libpayload: memmove: Don't make expectations of architecture memcpyJulius Werner
default_memmove() calls memcpy() when (src > dst). This is safe for the default_memcpy() implementation, but just calling memcpy() may invoke an architecture-specific implementation. Architectures are free to implement memcpy() however they want and may assume that buffers don't overlap in either direction. So while this happens to work for all current architecture implementations of memcpy(), it's safer not to rely on that and only rely on the known implementation of default_memcpy() for the forwards-overlapping case. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7ece4ce9e6622a36612bfade3deb62f351877789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24libpayload: Cache physical location of stringsNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates the remaining pointers that are not consumed by libpayload code, all of them strings. Also update the comment that `libsysinfo` only containts physical addresses. Change-Id: I9d095c826b00d621201c34b329fb9b5beb1ec794 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of CBMEM entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to CBMEM entries that are not consumed inside libpayload code. Change-Id: I3be64c8be8b46d00b457eafd7f80a8ed8e604030 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24libpayload: Cache physical location of cb_table entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to coreboot-table entries that are not consumed inside libpayload code. Change-Id: I95cb0af151e0707a1656deacddb8a5253ea38fc3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache copy of `cb_framebuffer` structNico Huber
Our AArch64 code supports dynamic framebuffer allocation which makes it necessary to change the framebuffer information during runtime. Having a pointer inside `libsysinfo` made a mess of it as the pointer would either refer to the original struct inside the coreboot table or to a new struct inside payload space. The latter would be unaffected by a relocation of the payload. Instead of the pointer, we'll always keep a copy of the whole struct, which can be altered on demand without affecting the coreboot table. To align the `video/graphics` driver with the console driver, we also replace `fbaddr` with a macro `FB` that calls phys_to_virt(). Change-Id: I3edc09cdb502a71516c1ee71457c1f8dcd01c119 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of serial-console structNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: Icd30e95c6b8115d16dd793914fb01a1a9da1854f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical CMOS option table locationNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: I64a37bef263022edb504086c02a3fd22ce068ba4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical cbmem console addressNico Huber
Same as with other consoles and drivers that cache an address outside the payload (e.g. video/corebootfb), we should store the physical address, so we can derive the virtual address on demand. This makes it save to use the address across relocations. As a first step in migrating `libsysinfo` to `uintptr_t`, we also switch to the physical address there. Fixes the default build of FILO, tested with Qemu/i440FX and Qemu/Q35. Change-Id: I4b8434af69e0526f78523ae61981a15abb1295b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-19arch/arm: Enable FIT payloadsSam Lewis
Implements fit_payload_arch for the arm (aarch32) architecture, so that FIT images can be used. The implementation is very similar to the existing implementations for arm64 and riscv, and has mostly been lifted from these other ports. TEST: Booted Beaglebone Black (in progress port, to be submitted soon!) with a FIT image containing a 5.4 kernel, dtb and initramfs. Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-18payloads/nvramcui: Fix `make clean`Nico Huber
After `make clean` a new build should not be based on stale artifacts. Hence we have to remove them. Change-Id: I540a83a6c87b843b1c4c9c55990bf3e91fe90d79 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18payloads/coreinfo: Fix `make clean`Nico Huber
After `make clean` a new build should not be based on stale artifacts. Hence we have to remove them. Change-Id: I18292c674986078d991668124193b6aa31234d47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17payloads/seabios: Update stable version to 1.14.0Elyes HAOUAS
see https://seabios.org/Releases Change-Id: I20e57314b867581f41921178ff1ffcbaa50a0843 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-17libpayload/defconfig: Set default heap size to 1MiBNico Huber
libpayload's drivers keep growing. With certain hardware/payload combinations (last time witnessed with Kontron/bSL6 and FILO), the default configuration runs out of memory. As there is a lot enabled by default, also set a big default heap size. Tested with FILO on QEMU/Q35. Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-13libpayload: cbgfx: Add color mapping functionalityYu-Ping Wu
Similar to set_blend(), add set_color_map() for mapping background and foreground colors of a bitmap. Also add clear_color_map() for clearing the saved color mappings. Note that when drawing a bitmap, the color mapping will be applied before blending. Also remove unnecessary initialization for static variable 'blend'. BRANCH=puff BUG=b:146399181, b:162357639 TEST=emerge-puff libpayload Change-Id: I640ff3e8455cd4aaa5a41d03a0183dff282648a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-28libpayload: Replace include/compiler.h with commonlib/bsd's versionPatrick Georgi
This ensures that it's available under BSD license terms. Change-Id: Ica13014b847473fee02516be0b27684c6cfb07bc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25payloads/libpayload/drivers/usb/usb.c: Remove whitespace before tabElyes HAOUAS
Change-Id: Iba73ae4d89cef94f238e9a74300f6088669f355b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/libpayload/curses/menu/eti.h: Remove unneeded whitespacesElyes HAOUAS
Change-Id: Ia77c5be4b22740f88fb9c11bff95036adbd8145f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/libpayload/arch/arm/cpu.S: Remove whitespaces before tabElyes HAOUAS
Change-Id: I2960f95937db23aa3a38ca64085728e6d10968f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/external/tint/Makefile: Remove whitespaces before tabElyes HAOUAS
Change-Id: Ie08e92778e029b962cf0ed5f95ab740458e82fc5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23libpayload: cbgfx: Add draw_line()Yu-Ping Wu
Add a function draw_line() to draw either a horizontal or vertical line segment. Theoretically a horizontal line can also be drawn by calling draw_rounded_box() with dim_rel.x being the line length and dim_rel.y being the line width. However, due to the truncation in integer division when converting relative coordinates to absolute ones, this will potentially produce inconsistent line widths, depending on the value of pos_rel.y. It is guaranteed that draw_line() will produce consistent line widths, regardless of the position of the line. Also, when the thickness argument is zero, this function is able to draw a line with 1-pixel width, which is not achievable by draw_rounded_box(). BRANCH=puff BUG=b:146399181, b:161424726 TEST=emerge-puff libpayload Change-Id: I2d50414c4bfed343516197da9bb50791c89ba4c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-07-21libpayload/xhci: Try harder to read 32-bit caps at onceNico Huber
With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI register issue) we restructured our capability register accesses because the compiler used the wrong access size. While we do use only 32-bit types now, a compiler may still try to be clever and optimize things in unexpected ways. So we add an explicit read32() now. For instance for the 8-bit MaxPorts field, in the most significant bits of `capreg + 4`, our read + mask + shift ((cap)->hciparams1 & 0xff000000) >> 24 was turned into a single 8-bit read instruction by GCC on x86: 31: 0f b6 52 07 movzbl 0x7(%edx),%edx Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-16libpayload: allow nonblocking delay and more than one delayRonald G Minnich
Extend the local APIC timer delay so that it can be started, and waited for, independently. Add an EOI so that more than one APIC timer interrupt is possible. Previous to this, because there was no EOI, the first timer interrupt the CPU took was also the last it would take -- apic_delay would only work one time. Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-15cbgfx: Add blend functions to calculate transparencyShelley Chen
Up until now we have no way of adding transparency into our firmware screens. Add set_blend() and clear_blend() functions to store alpha value and rgb values to calculate alpha blending in calculate_colors(). BUG=b:144969091,b:160839199 BRANCH=puff TEST=dut-control power_state:rec press ctrl-d Ensure background is dimmed when dialog pops up Change-Id: I95468f27836d34ab80392727d726a69c09dc168e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-15payloads/depthcharge: Makefile: resolve fail of concurrent buildMichael Niewöhner
Resolve missing dependency to fix concurrent building. Resolves: https://ticket.coreboot.org/issues/271 Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-12payloads/external: fix depthcharge build from sourceSelma BENSAID
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I17ae7450a9641268fe392bed0f24846abc8e6f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43203 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 17:54:46 +0000