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2015-04-17purin: add basic set of files for libpayloadDaisuke Nojiri
BUG=none BRANCH=tot TEST=emerge-purin libpayload depthcharge coreboot chromeos-bootimage Change-Id: I6a46067a288ecea352a2724c62c62066e3f4a383 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 355371317dde0546fbab2cd109bc17463f77c4fd Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I8c43acc4d270c3b2d7c18af07c077a553e3c6f6f Original-Reviewed-on: https://chromium-review.googlesource.com/245492 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: read register width from coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: sync arch/arm/cache.c with corebootDavid Hendricks
There was a recent patch by Deepa Dinamani applied to coreboot's cache.c which fixed a bug that occurred when icache is on but dcache is off ("arch: armv7: Fix cache sync instructions."). Although this bug is not likely to be encountered by the time libpayload is run, it's worth applying it to keep things in sync. BUG=none BRANCH=none TEST=n/a since we have icache and dcache enabled on all ARM platforms when libpayload is run. Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40 Original-Reviewed-on: https://chromium-review.googlesource.com/243276 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: Take flash parameters from corebootDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15Danger: Initial mainboard importDavid Hendricks
This adds a directory with files copied over from Brain along with build-related changes so that emerge-veyron_danger works. The next patch will account for other differences. BUG=none BRANCH=none TEST=emerge-veyron_danger coreboot works Change-Id: I7ebd431cd48e257dfa761d32013d0e251b4f155d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a0f7d2f96540df6fdcd7a99d9e0fa02bbc6c1f73 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id265a7715f07a647a449f00097bf40f7c9b4c068 Original-Reviewed-on: https://chromium-review.googlesource.com/241711 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Brain: Initial mainboard importDavid Hendricks
This adds a directory with files copied over from Jerry, in addition to build system related changes (configs/* and Kconfig stuff) necessary to emerge-veyron_brain coreboot. The next patch will account for differences between Jerry and Brain. BUG=none BRANCH=none TEST=emerge-veyron_brain coreboot works Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36 Original-Reviewed-on: https://chromium-review.googlesource.com/236989 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9637 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-14libpayload: avoid hanging on make junit.xmlPatrick Georgi
make oldconfig doesn't like 'y' as response to a choice item such as the architecture list. An empty response, however, is acceptable, so use that. Change-Id: Ic3164dd3f40e4a7f5d91e3a7008893655cd69ac2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9676 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14pistachio: modify timer to account for CPU counter overflowIonela Voinescu
Extended the 32bit CPU counter to 64bit by adding a static variable that takes into account CPU counter overflow. The varibale is updated everythime the timer_raw_value function is called so I assume that the function is called often enought to not miss an overflow of the CPU counter. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I98bcc56e600dcff0c6da7c140dd34faec5e00885 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 972b105f950d800fa44f27bce090f6b89a5a84b9 Original-Change-Id: Id67b14e9d9c2354bc417b6587b615d466690c9b7 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/247642 Original-Reviewed-by: Daniel Ehrenberg <dehrenberg@chromium.org> Reviewed-on: http://review.coreboot.org/9672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14arm64: Increase dma region size to 32MiBFurquan Shaikh
BUG=None BRANCH=None TEST=Download and write to kernel partition successful on ryu Change-Id: I9623a0a430e95633dabbb87537a5c70bc9619dde Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ba52d7c7baa42de3149cc604423a5825988401e Original-Change-Id: Ia6ba5ad52596c32cc3ad42f98c7f4f8b3e13d6c5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9661 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-14libpayload dwc2: use bus addresses for buffersIonela Voinescu
The address of the output buffer sent to the device should be the bus address and not the virtual address. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; USB works properly after this change BRANCH=none Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438 Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245387 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9455 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14libpayload dwc2: Use a new FIFO allocation methodhuang lin
Total FIFO length is split into 512 byte blocks. Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly. This method avoids hardcoding and makes the FIFO size value work for dwc2 controllers that have a different FIFO ram size. BUG=chrome-os-partner:32634 BRANCH=None TEST=Boot kernel from USB Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87 Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233119 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14libpayload: Add dwc2 usb driverhuang lin
BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211053 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
Non-x86 boards currently need to hardcode the position of their CBFS master header in a Kconfig. This is very brittle because it is usually put in between the bootblock and the first CBFS entry, without any checks to guarantee that it won't overlap either of those. It is not fun to debug random failures that move and disappear with tiny alignment changes because someone decided to write "ORBC1112" over some part of your data section (in a way that is not visible in the symbolized .elf binaries, only in the final image). This patch seeks to prevent those issues and reduce the need for manual configuration by making the image layout a completely automated part of cbfstool. Since automated placement of the CBFS header means we can no longer hardcode its position into coreboot, this patch takes the existing x86 solution of placing a pointer to the header at the very end of the CBFS-managed section of the ROM and generalizes it to all architectures. This is now even possible with the read-only/read-write split in ChromeOS, since coreboot knows how large that section is from the CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be changed on systems that place other data next to coreboot/CBFS in ROM). Also adds a feature to cbfstool that makes the -B (bootblock file name) argument on image creation optional, since we have recently found valid use cases for CBFS images that are not the first boot medium of the device (instead opened by an earlier bootloader that can already interpret CBFS) and therefore don't really need a bootblock. BRANCH=None BUG=None TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco. Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229975 Reviewed-on: http://review.coreboot.org/9620 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32Julius Werner
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-09libpayload: PCI bus scan - Eliminate endless loopLee Leahy
Don't attempt to scan the PCI bus if the bridge is disabled. When the PCI bridge is not setup and enabled, it is possible for the secondary bus register to contain the value zero (0). In this case the usb_scan_pci_bus routine gets into an infinite recursive loop which ends only when the heap or stack is exhausted. This patch verifies that the PCI bridge is enabled by verifying that it is enabled for either memory or I/O operations. When enabled, the secondary bus is scanned. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236382 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08libpayload: Add drivers for bg4cdDaisuke Nojiri
BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08arm: Dump additional fault registers in abort handlersJulius Werner
Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23libpayload: usb: xhci: set ENT flag in last Normal TRBSourabh Banerjee
If a TD is comprised of one or more Normal TRBs and terminated with an Event Data TRB, then the transition to the Idle state (and associated Stream state save) could occur after all the data for the TD has been moved (e.g. after Transfer Event TRBs have been executed), but before the Event Data TRB is executed. Under these conditions, the execution of the Event Data TRB is necessary to complete the TD, otherwise it does not occur until the next time the Stream is scheduled. This could lead to the lock up. The Evaluate Next TRB(ENT) flag provides a means of forcing the execution of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes the xHC to evaluate the Even Data TRB. BUG=chrome-os-partner:29375 TEST=Verified kernel boot-up on storm from previously failing USB stick. USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB Strontium Jet USB 3.0 Pen Drive 32 GB Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8 Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220123 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23libpayload: EHCI: Support root-hub TT featureJim Lin
If EHCI controller has TT (Transaction Translator) support in root-hub, then we need to keep control over this controller when USB keyboard (low-speed device) is connected to root-hub port. Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file (e.g. payloads/libpayload/configs/config.nyan_big) to support this feature. BUG=chrome-os-partner:32355 TEST=Tested on nyan_big platform. Press ESC+REFRESH+POWER keys on internal keyboard to power up. Press Left Arrow or Right Arrow on USB keyboard to switch between "English" and "Default Locale" in coreboot UI. Or unplug and plug in device and try again. Root hub <- low-speed USB keyboard Root hub <- full-speed hub <- low-speed USB keyboard Root hub <- high-speed hub <- low-speed USB keyboard Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220125 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23libpayload arm64: Allow board to define upper address limit on DMAFurquan Shaikh
Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8800 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-21libpayload: whitespace cleanupPatrick Georgi
Align struct members with tabs. Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: fix mmu_disable() cache problemHC Yen
The raw_write_sctlr_current() cannot be used in mmu_disable() because it pushes some registers to cached stack, and then just after cache disabled, the value was gone. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8799 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add helper functions with el argumentHC Yen
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8798 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: don't modify cbtable entriesAaron Durbin
The framebuffer structure lives in the coreboot tables. Those tables have a checksum calculation applied over all the entries. Therefore, one shouldnot be modifying fields within the coreboot table entries because the calculated checksum would be wrong. BRANCH=none BUG=chrome-os-partner:31936 TEST=On ryu, confirmed dev screen still works as well as cbmem utility once booted. Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16 Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230471 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8797 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Allocate framebuffer rangeJimmy Zhang
Allocate noncacheable memory for frame buffer and save base address to sys_libinfo. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226404 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Move console_init after post_sysinfo_mmu_setup callFurquan Shaikh
This is important since mmu is disabled during the post_sysinfo_mmu_setup call and calling printf can cause unaligned access. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt with console_init Change-Id: I5ef72ee449fdcf30186f97485cc532d6c56b2c5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 688ef3856d0502d057c9543ee7763601156e6385 Original-Change-Id: Ie376e394d084edd6c999fc9edde79f15a0264e7b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222664 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8795 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add function to get new range from available memrangesFurquan Shaikh
Provide a function to obtain a new memrange with requested properties (type, size, alignment, max_addr and other restrictions) from the set of available memranges passed in coreboot table. One user of this function would be getting memrange for dma, another one would be framebuffer. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic5a63ca2dca6c71f4ca2d77e2e2c8180d32a38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3cd75756e1405e044c029f2878bfcc9c8c962bdf Original-Change-Id: I187d73a4d55d3c6f49afbe9852901672d25de8dc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: fix mmu bugsAaron Durbin
1. keep functions and objects used entirely within mmu.c as static. 2. DMA region finding needs to terminate. Therefore, the next address to be attempted needs to be less then the current end address. 3. Ensure mmu_ranges passed to mmu_init_ranges_from_sysinfo() has 0 entries marked as used. BUG=chrome-os-partner:31634 BRANCH=None TEST=Booted ryu with RAM hole above cbmem tables below 4GiB. Change-Id: I71a9cb89466978aa63fca5d8bee97b8af75ea206 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 66518fd86e676bbddf52e9d9afdd76d72c8e2222 Original-Change-Id: I5cb4e5009359cb04c4e1b5fe60845f80fbdff02c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221725 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize and enable MMUFurquan Shaikh
What this change does: 1) Initialize limited page tables as soon as we jump into libpayload. Basically two ranges are initialized. One is for the BASE_ADDRESS and other is for the coreboot_tables. With page tables initialized and MMU enabled, we jump into code to parse coreboot tables. 2) Once coreboot tables are parsed and we have complete picture of the memory, we perform a complete page table initialzation and enable MMU and then jump to payload. Additionally, we also: 1) Initialize DMA memory on our own depending upon the memory map. It ensures that the DMA buffer is placed in 32-bit memory. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and we are able to start execution of libpayload in EL2 and reach kernel login prompt Change-Id: I8a6203e465868bc2a3e5cc377e108f36cc58e2fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7695bb7afe34ea460282125a0be440e8994b01e4 Original-Change-Id: Ie0f47b7759d4ac65a6920f7f2f7502b889afda6d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for read and write registers at current EL in ↵Furquan Shaikh
assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully for ryu Change-Id: I79241a944b68ebb24865e745a9835f54ab6d1a8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b55fbde466126c4de7f5f7bb2d1427196be842f Original-Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214576 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for mmuFurquan Shaikh
Adds support for initializing mmu, setting up dma areas and enabling mmu based on the memranges passed on in the coreboot tables. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: Id41a4255f1cd45a9455840f1eaa53503bd6fef3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2c6676bf51fcd85b61e9e08a261634a78137c4c Original-Change-Id: I217bc5a5aff6a1fc0809c769822d820316d5c434 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove dependency on coreboot tables for dma areasFurquan Shaikh
Libpayload should be able to setup its own dma areas and not depend on coreboot tables for passing this information. This patch and next allow libpayload to setup dma areas while performing mmu_init BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup properly with the mmu init patch Change-Id: I5f6fd19a957c7626a2bbe6b826c8987e64ed248f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f3552b8d3439a8b12d1e0b15ef67dcb14b8c96a Original-Change-Id: I44d9f394fa349abd7182c4ba10f1eaefd6e4fdaa Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216822 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add functions for reading memrangesFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: I12e7cdaf07c1bc4802a04dadd85384939b5a67e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c454a3d60b0e087df79de4fd9cff09596ae12ca5 Original-Change-Id: Iec82d56ae4a5f1ac6243afef1f453de3905d869c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216821 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8788 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove the DONT_USE_DC macroFurquan Shaikh
By default we dont want to use the special DC instruction. Thus getting rid of the DONT_USE_DC macro and enabling code appropriately in memset.S BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and memset works fine for mmu init Change-Id: Icb3193f4f0d122726dcdacbdcacbf53eba30e235 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 54f639ef2348acab54e32b18f6826a67bf52bc14 Original-Change-Id: Id89ec2c1731d21496eca617a3c03abaf48062908 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216820 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8787 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add functions for {read/write}_tcr_currentFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: I7a3dc9420fa85fa8f7ab70f0f55b200f432d3240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20c89d5df653ad65ad6d8ecc4c26de4c5e447564 Original-Change-Id: Ibd801ef1d777d306f35dde3c2b120af41d8f27e4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216819 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove tight-coupling with any particular ELFurquan Shaikh
Allow more flexibility by reading and writing to system registers at current EL. Instead of specifying what _ELx register to write to, code can specify _current. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles and boots to kernel on ryu Change-Id: Id38b675bfe67ca1e25f8c268192114e3f0bee800 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d4d07e26fc964dc3aaebfe03db59596d90093e9 Original-Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214577 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add library helpersFurquan Shaikh
Add library helpers to access standard arm64 registers. This library also provides functions to directly read/write register based on current el. So, rest of the code doesnt need to keep checking the el and call appropriate function based on that. BUG=chrome-os-partner:31634 BRANCH=None TEST=Libpayload and depthcharge compile successfully for ryu Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510 Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214575 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc generates and handles exceptions properly Change-Id: If3ecab93be6d02942b52960ec97edc687bedf64b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bba2caae0bd436ba9e5215f5d8606ce8c4987c98 Original-Change-Id: I4abe8a0e426eab2532852179dbb32505353cd0a1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214609 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize exception stackFurquan Shaikh
Initialize exception stack to be able to handle exceptions properly BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc successfully generates and handles exceptions on ryu Change-Id: I19163fae080b9ac3297a7ffe404446e427bf9a1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99157687c5178c3b3eb79f5589343db1b2b4cc86 Original-Change-Id: I4dc83ff32c1665e22127bf0b1e6d4c6b45c07a4a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214608 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add console_init to enable console logsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles sucessfully and hello libpayload seen on screen Change-Id: If312e005e306f7f70138aa27d2ef5b39620ec91e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d6aa84d7255d33e085f12c609f32309521ff58e Original-Change-Id: I73f888a7b8aa0065c1ca0bf7857c445cc5678cdc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operationsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: mips: add SOC CPU frequencyIonela Voinescu
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: mips: correct platform IDIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8745 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: pistachio: fix timer implementationIonela Voinescu
timer_raw_value must return the number of CPU ticks, and not the time obtained by dividing the ticks by the CPU frequency. The CPU counter is increased at every 2 CPU clocks and therfore the number of ticks will be the counter value multiplied by 2. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; it works properly. BRANCH=none Change-Id: Iae62cb328e882f84822250bdf72146321ca9bbe0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ab25ce7dcaffb453ee774d870963a56444d46af Original-Change-Id: I74408950900463a2c054d5aebd3edb005a325adb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8744 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: mips: add memcmp to the MIPS string functionsIonela Voinescu
The default string functions work with multiple of 4 bytes (sizeof(unsinged long)); MIPS will use LW/SW instructions for these operations and if the source and destination addresses are not aligned it will trigger an exception. Therefore, this implementation does all data access operations per byte, because there is no guarantee that the provided strings are properly aligned. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected BRANCH=none Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241885 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu
Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: cbfs: Fix ram_media map() error return valueJulius Werner
The correct return value for errors on a cbfs_media->map() call is CBFS_MEDIA_INVALID_MAP_ADDRESS, not NULL. Not sure if that's the best choice (since 0xffffffff is probably a more likely valid address than 0 there), but that's what the upper layers expect right now. BRANCH=veyron BUG=None TEST=Press CTRL+L with an RW_LEGACY section filled with 0xff. Observe how cbfs_get_header() returns failure without doing a bunch of NULL pointer accesses first (not that those have any visible effect on Veyron, but that's another problem...) Change-Id: I3d012fc9af9da6e01159990a6bdd62c38fc22329 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a609e17bb9b0ef4d3a833f72fa4fbfd8e8cb0ab Original-Change-Id: I0793434116a8c568e19fe0dee24f13942fc50f25 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238991 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/8758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: Add RAM code to sysinfo_tDavid Hendricks
This adds CB_TAG_RAM_CODE and an entry to sysinfo_t. BUG=chrome-os-partner:31728 BRANCH=none TEST=Built and booted on pinky w/ depthcharge patch and saw that /proc/device-tree/firmware/coreboot/ram-code contains correct value Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f Original-Reviewed-on: https://chromium-review.googlesource.com/231132 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: Add support for parsing RAMOOPS range from corebootFurquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. ramoops console log verified after causing kernel to fault. Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6 Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228742 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: make wifi calibration table available through sysinfoVadim Bendebury
The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8753 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 00:50:59 +0000