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2014-08-01armv7: add wrapper for DCCSW (data cache clean by set/way)David Hendricks
This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Use coreboot’s serial console settingsMartin Roth
Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Update makefile for olddefconfigMartin Roth
Instead of creating the SeaBIOS .config file for QEMU, then changing things to be coreboot specific, create a default config for coreboot, then run olddefconfig to use the SeaBIOS defaults as they're set for coreboot. This leads to a cleaner config. Note that CONFIG_THREAD_OPTIONROMS defaults to enabled for SeaBIOS if we're building for coreboot, so I reversed the logic. I *ASSUMED* that leaving CONFIG_QEMU_HARDWARE=y and CONFIG_DEBUG_IO=y previously was an oversight. If this is not correct, please let me know and I'll add them it back in. SeaBIOS disables these by default if building for coreboot. Change-Id: I42c6a56205bb15c6693a5f3a716b7876a4d78abe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6362 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31libpayload: provide missing cbfs symbolAaron Durbin
The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Old-Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit d3410c28ef9f37b832e2fa2d18351dda332bc9f7) libpayload: place dummy_media.c in correct object list The commit introducing dummy_media.c was placed in the libc object list. This wasn't correct. It should be in the libcbfs object list as well as guarded by CONFIG_CBFS. Old-Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56925 (cherry picked from commit 7937c7c5e95a934593bc0cedd5f4496b4770c303) Squashed two related commits. Change-Id: I84cd132b44cc2ea5b29acf109a3562baaeede9c6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6411 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12mainboard: Add new board Google PantherMohammed Habibulla
(Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer) BUG=chrome-os-partner:23563 TEST=emerge-panther chromeos-coreboot-panther [pg: Drop configs/, which is chromeos stuff, adapted libpayload's config.panther to work with upstream] [pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options] [pm: rebase to master branch of coreboot upstream] [md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set] Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174555 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5990 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Drop obsolete setting of reg_base in [oex]hciNico Huber
Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6251 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Catch null-pointer dereference in xHCINico Huber
Fix a possible null-pointer dereference (hopefully) before anyone runs into this. Also don't switch ports to xHCI if initialization failed. Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6245 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: xHCI: Always initialize controller->pcidevNico Huber
As the controller structure is never fully cleared, this one wasn't initialized for non-pci controllers (but checked for non-null later). Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6246 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Use unsigned long for BARs in *hci_init()Nico Huber
Using void* for physical addresses leads to much casting and confuses developers when to convert from physical to virtual addresses or the other way around. When using plain integers for physical addresses and pointers for virtual addresses things become much cleaner and we won't ever end up dereferencing a physical address. Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6244 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Keep physical addresses in console driversNico Huber
Like done in FILO, libpayload's console drivers might be initialized before a relocation. So keep physical pointers in there which won't break on relocation. Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6247 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Remove redundant phys_to_virt() from xHCI driverNico Huber
Remove a redundant phys_to_virt() that sneaked in the initialization of PCI xHCI controllers. The use of casts from void* to u32 (and vice versa) prompts for things going wrong here. That will be addressed in a later commit. Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6243 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-28payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4Paul Menzel
SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other things, supports writing debug messages to CBMEM console. The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the SeaBIOS configuration file `.config` as otherwise the SeaBIOS build from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is detected as a new option. This option was already added and enabled in commit 7c1a49bc [1] SeaBIOS: have coreboot pass the choice to run optionroms in parallel so SeaBIOS messages are now written to the CBMEM console. Successfully tested on the Asus M2V-MX SE. [1] http://seabios.org/Releases [2] http://review.coreboot.org/5443 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5093 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23payloads/coreinfo/multiboot_module.c: Trivial fix indentsEdward O'Callaghan
Stylistic fix-up's. Change-Id: I0cad7c860280d0d8dcb16d052846c72f690e2b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5731 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-17libpayload: Fix to properly disable serial consoleKyösti Mälkki
With coreboot builds with serial console disabled, there is no CB_TAG_SERIAL entry in coreboot tables. We ended up with lib_sysinfo.serial == NULL and serial_hardware_is_present == 1. Change-Id: I9a2fc0b55bf77769f2f2bfbb2b5476bee8083f7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5723 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09payloads: make build system integration work againPatrick Georgi
Payloads using Kconfig get confused by coreboot Kconfig configuration in environment variables. Prune them. Change-Id: I63da2af0a15dca35d70cd65b2f74a1564aab9483 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5710 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-09payloads/coreinfo/README: Use `It is` instead of `Its`Paul Menzel
Change-Id: Ic1a9f2f01c26ee97cd7183fcf1755cb916f1b02e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5704 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.Edward O'Callaghan
Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16filo payload: Fix the buildPatrick Georgi
Also strip down the config that's set since these are actually SeaBIOS options, not FILO... Change-Id: I5dbe6255996f9e115699ff2a83fb3450533520ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4647 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-07SeaBIOS: have coreboot pass the choice to run optionroms in parallelIdwer Vollering
Introduce the tunable CONFIG_SEABIOS_THREAD_OPTIONROMS. Change-Id: Ifd4d9fca7316eb739ff184e54bdc1cdb0262f0c6 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5443 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-15libpayload/ahci: Fix a warning by decompartmentalise the AHCI driver.Edward O'Callaghan
Decompartmentalise AHCI driver into two parts, ATA and ATAPI. Add a few superficial comments while here. This also fixes a compiler warning. Change-Id: Ia1fd545b39868a81cbc311f6ffc786f9f1f61415 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-30libpayload: Parse CBMEM ACPI GNVS pointerDuncan Laurie
Pull the ACPI GNVS pointer from CBMEM and expose it in the sysinfo structure for use by payloads. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I47c358f33c464a4a01080268fb553705218c940c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28libpayload: adjust max number of memrangesAaron Durbin
Rambi currently has more than 16 memory ranges. Because of this libpayload is silently dropping them and the full amount of memory is not being properly wiped. Correct this by bumping the number of ranges to 32. BUG=None BRANCH=None TEST=Built and booted rambi. Noted that the full amount of memory was being properly wiped. Change-Id: Ida456decf2498cb1547c0ceef23df446a975606b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175792 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4942 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-26Revert "Makefile: Check $CC variable returned from xcompile is not empty."Alexandru Gagniuc
This reverts commit 1287d1cc80c52ff2598f2bae235fc42d8456f44a. This commit has the side-effect of making abuild fail, and as such is reverted until a safe solution can be found. Change-Id: Ib8cb78468c2922322b490e0b52c0bd24f3de7ef9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3269 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-23Makefile: Check $CC variable returned from xcompile is not empty.Andrew Wu
If xcompile can't find out suitable GCC compiler for i386/armv7, it will not set $CC_i386/$CC_armv7 variable. Makefile sets $CC variable from xcompile, and will print strange error messages when executing $CC program if $CC is empty. Add checking to avoid this problem. If $CC is empty, also delete invalid .xcompile file, so Make can recreate this file next time. Change-Id: Ia8d481d76ca52f3351cb99f05779d06947161c5d Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3905 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-19nvramcui: Trim values when setting.Vladimir Serbinenko
Values get space-padded by curses and then enum search fails to match them. Rtrim to compensate for curses. Change-Id: Iecf095f21cfade9425eaa039b67625615eb80481 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4692 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-01-19libpayload/lpgcc: Add curses include path.Vladimir Serbinenko
Without it payloads that need curses fail to build. Change-Id: I4533238b547e4c2d9e0778fb7d314db35a9559df Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4689 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-19libpayload/options: Fix out of array read.Vladimir Serbinenko
It resulted in garbage in upper bytes of numeric options. Change-Id: I5e5d8b770ed93c7e8a1756a5ce32444b6a045bac Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4691 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-19libpayload: Bring keyboard_wait_write() backPatrick Georgi
Code is using it... Change-Id: I6894b45cbbf70c8e7ce37ce18d93cadf0ea9fbfc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-08libpayload: add junit.xml build targetPatrick Georgi
It builds all defconfigs/* and logs the results in junit.xml, suitable for consumption by jenkins Change-Id: I86c4022851b47820c95359b2ea9b735a77b1bc2c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08libpayload: update defconfigPatrick Georgi
Just clean out stuff we don't even have anymore Change-Id: I2b4128c6496b4400d52d87680bedc3cece3d444c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4550 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08libpayload: reintroduce optional PCI in XHCI driverPatrick Georgi
being a good citizen on the box, libpayload tries to return to EHCI mode on shutdown, so a non-XHCI capable USB driver after it (eg. in the OS) finds something to work with. Change-Id: Id227d646e08a258b841c644263112f0815dd486c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-21armv7: add wrappers to read/write L2ACTLRDavid Hendricks
This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21arm: libpayload: Include stdint.h in cache.hGabe Black
The cache.h header uses standard int types but doesn't include stdint.h itself. Change-Id: If470978164b0cd1f05c27c2c8eda365133cc47ff Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63190 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4387 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Libpayload: Add keyboard-disable function.Martin Roth
Add a function to disable and clear the keyboard controller. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I3e1f011c3436fee5ce10993c6c26a3c8597c6fca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63627 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4395 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21libpayload: Include hexdump.c in the Makefile so it gets builtGabe Black
The hexdump function was added to libpayload recently, but its source file was never added to the Makefile so it wasn't compiled or linked in. Change-Id: Ic3c12a5b8a6ea631b83c10a6e4210544ff00b5bf Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64878 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21libpayload: Increase USB EHCI transfer timeoutJulius Werner
The EHCI driver defines a maximum transfer timeout of two seconds. The comments state that during tests the maximum amount of required transfer time was for the SCSI TEST_UNIT_READY command on certain devices. We have now observed a USB device (Patriot Memory 13fe:3100) that can NAK this command for slightly more than two seconds. It will also completely fail if the timeout hits, since it gets confused by the subsequent CSW retry/recovery mechanism and starts producing babble errors. This patch increases the timeout to three seconds to circumvent this problem. To test, boot a Falco from a red-black RageXT USB stick. Change-Id: I3c4fef468fb16eacc5a487d76d025a78fb450e27 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/4379 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-16libpayload: Add simple hexdump functionRonald G. Minnich
- prints hex and ascii - detects duplicate all zero lines Change-Id: I084b3072bc05725b23c5c3ca0dbf1533f164a08c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63660 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Author: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/4393 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-12libpayload: expose cbfs ram functionsAaron Durbin
The ram_media.c file is being compiled, however the global functions were not exposed through a header. Change-Id: I4588fbe320c29051566cef277bf4d20a83abf853 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56642 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4194 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12libpayload: Get rid of a compiler warningGabe Black
Change-Id: I7252925ef5c4efb69cad6b6fa179031162cf8e74 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61058 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12libpayload: armv7: Add cache control function to invalidate range.Hung-Te Lin
When dealing with DMA, we need a function to invalidate cache without corrupting contents on main memory (clean). Change-Id: I28e632ae57a7b7ed1accee74e76045b92f92a699 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61078 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12payload: armv7: Fix dcache_clean_by_mva.Hung-Te Lin
The OP assigned by dcache_clean_by_mva must be handled in dcache_op_mva. Change-Id: Ib32262f0419453b2690d7c1a1c6602380b46a37f Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61077 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4344 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-06Do not export variables to GRUB buildVladimir Serbinenko
Variables in coreboot and not in line with GRUB ones. E.g. HOSTCC is both HOST_CC and BUILD_CC for GRUB (consult INSTALL for more details) and what coreboot calls CC is TARGET_CC for GRUB. Current code plugs this by defining variables explicitly but it has a nasty effect that make stops caring about flags added in makefile itself. Undef as many variables as possible but still pass them to configure for them to have correct effect and keep CC assignment as my make version doesn't undefine it even when instructed to do so. Tested with qemu. Change-Id: I9d18f557138a20ae3918d698dee8f5b5c5738f75 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-05libpayload: Have similar cache api on ARM and x86Stefan Reinauer
So far this is used by the USB driver, and instead of having ifdefs all throughout that code, implement the same API on x86 and ARM. Change-Id: I8093ad818ad2e38a0901787aa8674faf591d580c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56105 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4320 Tested-by: build bot (Jenkins)
2013-12-05libpayload: Clean up CFLAGSStefan Reinauer
- Add -ffreestanding and -fomit-frame-pointer for all platforms. - Add ARMv7 specific flags to the armv7 Makefile Change-Id: I71ab1b096e505940cc20c266bccd43917bcfad3a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56104 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4317 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05libpayload: sync ARMv7 arch/io.h with corebootStefan Reinauer
On ARMv7 we need to carefully add memory barriers to all memory read and write operations. This change brings libpayload in sync with what coreboot is doing. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c30b0f0d30531c5f9d99c2729246a86b8cec26 Reviewed-on: https://gerrit.chromium.org/gerrit/59294 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03Drop obsolete CONSOLE_LOGBUFStefan Reinauer
This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4256 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03libpayload: ARM: Don't leave alignment checking on after the exception testGabe Black
Currently, the exception handling code on ARM in libpayload turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Built and booted into depthcharge on pit with an unaligned accesses added after the call to exception_init in the depthcharge's main. Before this change, the access caused an exception. After this change, the access completed successfully. Change-Id: If92cab3cc8eabca7c5b0560ce88a8796a27fe3b2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59372 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4255 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03libpayload: Make the region to scan for the cb tables configurable.Gabe Black
The address range to scan for the coreboot tables varies from machine to machine based on the range memory occupies on the SOC being booted and on the amount of memory installed on the machine. To make libpayload work on different ARM systems with different needs, this change makes the region to scan configurable. In the future, we might want to come up with a more automatic mechanism like on x86, although there's less consistency on ARM as far as what ranges are even memory in the first place. Change-Id: Ib50efe25a6152171b0fbd0e324dbc5e89c527d6e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59242 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4254 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
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