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2018-10-15tianocore : Enable Serial Debug for UEFI payload Debug buildWonkyu Kim
Change-Id: I29953250ca278d5b1977be3763359df5110f67c7 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/29004 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15libpayload: Always set pciaddrPatrick Rudolph
For debugging purposes always set the pciaddr attribute. Tested on Lenovo T500. Change-Id: I83a0e7f7196ed251fa0becc4e56bef3ca68f20f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12libpayload: arm64: Add GDB supportJulius Werner
This patch adds remote GDB support for the arm64 architecture. Change-Id: I2fa4dbca6c39f822f489a5e81bd052f53fda98a5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12libpayload: gdb: Factor out gdb_handle_reentrant_exception() from arm32Julius Werner
The arm32 GDB architecture code contains a little hack that allows it to (sort of) correctly deal with a reentrant exception triggered from within the GDB stub. The main logic for this isn't really arm32 specific and could be useful for other architectures as well, so factor it out into a separate function. Change-Id: I3c6db8cecf1e86bba23de6fd2ac9fdf0cf69d3c6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12libpayload: arm64: Make exception handling closer to arm32Julius Werner
This patch reworks the arm64 exception handling to be more similar to how it works on arm32. This includes a bunch of features like actually saving and restoring more exception state in the exception_state structure and supporting the same sort of partial reentrancy that is useful for GDB. Since there's no instruction to directly load into or store out of SP on arm64, we can't do quite the same thing where we use that to read an exception_state_ptr variable right after exception entry when no other register is available. But we can do something very similar by (ab-)using the "high" stack pointer (SP_EL2) as a pointer to the exception_state struct and providing a function to change it. Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner
This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-10-11payloads/tianocore: Fix not applying patch 06_CorebootPayloadPkg_keep_cb_tablePiotr Król
Mentioned patch could not be applied in coreboot-sdk:1.52. With this fix patch apply correctly. Change-Id: I130856520f91bcfbd9a62741b1d5abb6495a6eac Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-09payloads: Only show supported payloads in menuconfigPhilipp Hug
Some payloads don't depend on their supported platforms, which makes them visible in menuconfig even if they are not supported (yet). Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05LinuxBoot/arm64: Remove firmware from defconfigPatrick Rudolph
The extra firmware is not part of upstream kernel. Fixes build error if the firmware is not present. Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-04libpayload/x86/exception: Add ability to ignore unknown interruptsRaul E Rangel
This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/x86/exception.c: Remove exception_install_hookRaul E Rangel
Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Register a spurious interrupt vectorRaul E Rangel
We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Only ACK interrupts triggered by the APICRaul E Rangel
Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01libpayload/drivers/usb: Fix leaksPatrick Rudolph
Don't leak buffers on device detach. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01libpayload/drivers/usb: Fix broken retry counterPatrick Rudolph
Exit on first sucessful CONTROL transfer instead of doing GET_DESCRIPTOR_TRIES iterations. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-28payloads/tianocore: ignore whitespace change when applying patchesPiotr Król
This change is required to apply patch 06_CorebootPayloadPkg_keep_cb_table since conflict in white space between patch and target file in edk2 makes patch rejected while building under coreboot-sdk:1.52. Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-26payloads/Kconfig: do not show compression menu for FITAndrea Barberio
FIT payloads do not support compression. Currently this would thrown an error like the following: E: FIT images don't support whole-image compression, compress the kernel component instead! With this patch, menuconfig will correctly *not* show payload compression for FIT payloads, and this will correctly set compression to NONE. Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Signed-off-by: Andrea Barberio <insomniac@slackware.it> Reviewed-on: https://review.coreboot.org/28732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-16payloads/external: Add yabits payloadMartin Roth
Yabits (Yet another UEFI bootloader) is designed to be a slim and quick alternative to Tianocore. It is still under heavy development. https://web.archive.org/web/https://yabits.github.io/ Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/28590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-14rampayload: Add the linuxcheck payloadRonald G. Minnich
The i386.c file uses standard 3f8 UART for some simple diagnostic prints, and the libpayload console otherwise. This payload was used to debug Linux as a rampayload and was very helpful for that work. Change-Id: I1cce5528780cd825fd91a88137fa70abd9f218e7 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28600 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-13payloads/tianocore: Add option to use 8254 timerLijian Zhao
Change TianoCore payload default to use HPET timer. Add an option to use 8254 timer for legacy platform support. BUG=N/A. TEST=Build and boot up into UEFI shell on Whiskey Lake rvp platform. Change-Id: I857704b0ca128fc9da193ae26a33c7cf89ad7320 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-09-12libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is longRaul E Rangel
This reduces power consumption on grunt by over 3W when sitting at the depthcharge recovery screen. BUG=b:109749762 TEST=Booted grunt in the recovery screen and made sure it continued to work. Change-Id: Id079c099ee4cf6a07724241af4400063f4551668 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28245 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Julius Werner <jwerner@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12libpayload/x86/delay: Add an x86 arch_ndelayRaul E Rangel
This method has a pause instruction to help the CPU relax a little bit. Measuring grunt it saves about 80mW. BUG=b:109749762 TEST=Made sure that grunt boots. Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28244 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12libpayload/libc/time: Add an arch_ndelay()Raul E Rangel
Replace _delay with an arch_ndelay(). This way each arch can setup their own delay mechanism. BUG=b:109749762 TEST=Verified delay's still work on grunt. Change-Id: I552eb30984f9c21e92dffc9d7b36873e9e2e4ac5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28243 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12libpayload/x86/apic: Add an apic_delay method and calibrate the timerRaul E Rangel
The apic_delay method will halt the CPU and wait for a timer interrupt to fire. I went with usec because nsec is too granular to guarantee. This method will be called from an arch_ndelay() method when the delay is large enough to justify a sleep. BUG=b:109749762 TEST=Tested it on grunt by changing the _delay method to call apic_delay(). Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12libpayload/arch/x86: Add support for initializing the APICRaul E Rangel
This is just the bare minimum required to initialize the APIC. I only support xAPIC and chose not to support x2APIC. We can add that functionality later when it's required. I also made the exception dispatcher call apic_eoi so that the callbacks won't forget to call it. BUG=b:109749762 TEST=Booted grunt and verified that depthcharge continued to function and that linux booted correctly. Also verified GDB still works. Change-Id: I420a4eadae84df088525e727b481089ef615183f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10libpayload/x86/gdb: Migrate to use set_interrupt_handlerRaul E Rangel
BUG=b:109749762 TEST=Verified GDB still functions by hitting Ctrl+G on the developer screen and stepping through some code. Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10libpayload/x86/exception: Add ability to handle user defined interruptsRaul E Rangel
I need to setup the APIC timer to fire interrupts. I would like to reuse the existing interrupt table. So I extended it to support user defined interrupts. I just added all 255 vectors so there wouldn't need to be any additional build time configuration. I'm going to deprecate exception_install_hook and remove it in a follow up. It will be replaced with set_interrupt_handler. This way the exception lookup does not have to manage a list of callbacks, or have to worry about the order they are processed. BUG=b:109749762 TEST=Wrote an interrupt handler and fired an APIC timer interrupt and verified that vector 32 was returned. Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-04payloads: Remove/fix trailing whitespaceMartin Roth
Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1 Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/28430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04payloads/LinuxBoot: Fix remaining issuesPhilipp Deppenwiese
* Update kernel versions * Fix initrd path handling Change-Id: Ia0641fd0c0db1e47ee4829b73871af662d4a6370 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-23libpayload/x86/exception: Add methods to enable/disable interruptsRaul E Rangel
Will be used by the APIC. BUG=b:109749762 TEST=Verified by the other cls in the stack. Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23libpayload/x86/cpuid: Add a cpuid macroRaul E Rangel
Since libpayload doesn't link against libgcc we need to define our own cpuid macro. I didn't add any error checking since anything in the last decade should support cpuid. BUG=b:109749762 TEST=called it and made sure the correct flags were returned. Change-Id: Id09878ac80c74416d0abca83e217516a9c1afeff Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22payloads/external/Memtest86Plus: allow for selecting a specific revisionStefan Tauner
Because the Kconfig configuration files for primary payloads are already sourced via a wildcard pattern this change requires to use another file name pattern. Change-Id: I83b89f5e14618e8a487ebb044fcdd3c175662591 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14cbmem: rename vdat to chromeos_acpiJoel Kitching
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10linuxboot: remove curley brace expansion from u-root commandsDavid Hendricks
Curley brace expansion is a bash-ism, so we can't use it for the u-root command list. This unfortunately also breaks the current Kconfig option since the list needs to be separated by space instead of commas. Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/27967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08libpayload/drivers/usb/xhci: Replace raw values with constantsRaul E Rangel
BUG=none TEST=compiled on grunt and made sure USB still works in depthcharge Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06payloads/external/SeaBIOS: add support for sercon portPiotr Król
Change-Id: Id2d2ed0fa97f2cef5818a8508bb8ee3ddba73647 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/26060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-06exception: Fix segment error code maskRaul E Rangel
The segment error descriptor is actually 13 bits long. BUG=b:109749762 TEST=Verified by causing a segment error Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31payload/LinuxBoot: Fix compilation and clean targetPhilipp Deppenwiese
* Update kernel version * Add kernel directory removal during clean target * Add x86 and x86_64 default configs Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27745 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20libpayload/arm64: Drop unused static arrayPatrick Georgi
Fixes build with gcc8.1 Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-19payloads/LinuxBoot: Add ARM64 supportPatrick Rudolph
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures. * Always compress kernel Image using xz * Create FIT uImage containing the kernel, initramfs and DTB * Add ARM64 defconfig for all SoCs Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17libpayload/generic_hub: Detect port disconnect after resetRaul E Rangel
If a port disconnects after a reset we should abort any initialization on the port. This might mean the device has re-enumerated as a 3.0 device so the hub should be scanned again. BUG=b:76831439 TEST=Verified USB-C devices that get detected correctly in depthcharge. Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17libpayload/xhci: Check noop return code when debuggingRaul E Rangel
Make it obvious that the command has failed. BUG=b:76831439 TEST=Verified on grunt Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17libpayload: Add UNKNOWN_SPEED to usb_speed enumRaul E Rangel
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum is unsigned so this results in a positive value which implies success. Adding a -1 to the enum will make it signed so the >= 0 check will work correctly. BUG=b:76831439 TEST=verified on grunt that -1 is returned when port is disabled. Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-16libpayload: Make libpayload compile using gnu11Raul E Rangel
This matches coreboot. BUG=b:76831439 TEST=emerge-grunt libpayload deptcharge chromeos-bootimage then booted image Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-16libpayload/xhci: Document struct offsets on xhci_tRaul E Rangel
This makes it easier to know what offset each register references. BUG=b:76831439 TEST=none Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-10payloads/Kconfig: Put option *None* at the topPaul Menzel
As *None* is special and not a payload, it makes sense to put it at the top. Also, it was at before the latest addition of the FIT payload choice. Fixes: a892cde6 (lib: Add FIT payload support) Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-07-06payloads/seabios: Update stable from 1.11.1 to 1.11.2Martin Kepplinger
SeaBIOS 1.11.2 was tagged with the following changes: ``` f9626cc cbvga_set_mode: refine clear display logic f88297a qemu: add qemu ramfb support a2e4001 vgasrc: add allocate_pmm() 17b01f4 pmm: use tmp zone on oom 44b17d0 bochs_display_setup: return error on failure 4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator. dd69189 cbvga_list_modes: don't list current mode twice 5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140 961f67c qemu: add bochs-display support 767365e cbvga: factor out cbvga_setup_modes() 7906460 optionrom: enable non-vga display devices ``` Tested by running it on a Thinkpad X230. Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0 Signed-off-by: Martin Kepplinger <martink@posteo.de> Tested-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/27326 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-03payloads/iPXE: add iPXE serial enable optionMichał Żygowski
Since SeaBIOS 1.11.0 implements serial console and etc/sercon-port runtime config file is present in CBFS, SeaBIOS additionally redirects iPXE output to configured IO port. For boards which use the same UART for SeaBIOS and iPXE console it causes doubled output. The option is enabled by default and passes UART configuration to iPXE Makefile as before. When unselected, only SeaBIOS handles printing output from iPXE. Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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