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2020-04-20libpayload: Make 8250 UART driver relocation safeNico Huber
`lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Accessing the wrong value during relocation of FILO resulted in a hang with DEBUG_SEGMENT and UART console enabled. Work around that by caching the whole table entry locally. An alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reto Buerki <reet@codelabs.ch> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14lp/drivers/usb: Work around QEMU XHCI register issueDuncan Laurie
The QEMU XHCI controller does not support byte/word reads from the capability register and it expects dword reads only. In order to make this work move the access of the capability register fields to use macros instead of a packed struct bitfield. This issue was filed upstream: https://bugs.launchpad.net/qemu/+bug/1693050 The original fix attempt in 2012 was not effective: https://github.com/qemu/qemu/commit/6ee021d41078844df60a3a466e3829a3e82776f3 With this change the controller is detected properly by the libpayload USB drivers. Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09payloads/nvramcui: Select USE_OPTION_TABLEMatt DeVillier
nvramcui requires use of CMOS for NVRAM configuration, so depend on HAVE_OPTION_TABLE and select USE_OPTION_TABLE to ensure that nvramcui is actually functional when included in a build. Change-Id: I0595514f636b8ce67bbc789ecc96a93c99068c50 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-03libpayload: malloc: Change memcpy() to memmove() in reallocJulius Werner
Our realloc() works (somewhat suboptimally) by free()ing the existing allocation and then reallocating it wherever it fits. If there was free space before the old location, this means the new allocation may be before the old one, and if the free space block is smaller than the old allocation it may overlap. Thus, we should be moving memmove() instead of memcpy() to move the block over. This is not a problem in practice since all our existing memcpy()s are simple iterate and copy front to back implementations which are safe for overlaps when the destination is in front of the source. but it's still the more correct thing to do (in case we ever change our memcpy()s to do something more advanced or whatever). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-01cros_ec: add chrome EC headers to include pathCaveh Jalali
This adds the path to chrome EC headers to the depthcharge build. Depthcharge currently includes a manually maintained copy of the EC headers which are perpetually out of sync with the real interface definitions. By adding the include path, we can build depthcharge with the actual EC interface definitions and eliminate the manual maintenance of copies of EC headers. Once the include path is in place, we can remove the copies of the EC headers from depthcharge. BUG=b:152373049 Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-03-23libpayload/drivers/nvram: Fix coding stylePatrick Georgi
If one branch has braces all should have them. Change-Id: I94e70c6c6188768d9b37a2d154f4d5b8af31f78c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39396 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23libpayload/drivers/nvram: Add function to write RTCPatrick Rudolph
Add a function to set the RTC to provided struct tm. Change-Id: I17b4c1ee0dcc649738ac6a7400b087d07213eaf0 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10libpayload/corebootfb: Replace obsolete macros FI and CHARSNico Huber
These macros serve no purpose anymore, let's do the substitution manually once and for all. Also update the comment on the macros and fix whitespace on the touched lines. TEST=Checked that there are no changes in compiled code. Change-Id: Ib60f9ab157e2e7d44b551dd4f695a6c25ebeb405 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-09libpayload: Add uart/serial driver support for trogdorT Michael Turney
Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09libpayload: Improve rtc functionsPatrick Rudolph
On Lenovo T500 the RTC readings where wrong, as RTC has different encodings, depending on the statusB register. Support BCD vs binary RTC format and AM/PM vs 24h RTC format. Fixes wrong date and time on Lenovo 500. Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09libpayload/corebootfb: Add option to center a 80x25 consoleNico Huber
This makes payloads which are hardcoded to a 80x25 console look much better, e.g. FILO with its "GRUB" user interface. Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09libpayload/corebootfb: Keep local copy of framebuffer infoNico Huber
Keeping a local copy of the framebuffer info allows us to make changes, e.g. add offsets. It also avoids trouble with relocation. Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-04libpayload: add read64() and write64()Thomas Heijligen
Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03payloads/ext/Makefile.inc: Fix SeaBIOS race conditionAngel Pons
For a very long time, SeaBIOS sometimes failed to build when using multiple threads. This known problem has been haunting everyone for a very long time. Until now. Unlike most other payloads, building SeaBIOS results in two files: the SeaBIOS payload itself and SeaVGABIOS. Each file has its own target, and there's a third target called "seabios", which has the same recipe as the SeaBIOS file, which calls `payloads/external/SeaBIOS/Makefile` with a bunch of arguments. In addition, SeaVGABIOS depends on "seabios". When executing serially, if the file of either SeaBIOS or SeaVGABIOS is needed, the SeaBIOS Makefile will be run. This will generate both files, so it is not necessary to run the Makefile more than once. However, when using multiple threads, it can happen that one thread wants to make the SeaBIOS file, while another one wants to make the SeaVGABIOS file, which depends on "seabios". This implies that both threads will execute the SeaBIOS Makefile at about the same time, only to collide when performing git operations. Since git uses a lock file when updating the index, one of the threads will fail to acquire the lock with an error, which will ultimately cause the build to fail. Whenever this happened, manually aborting with Ctrl-C made the build process fail again because of the same error. The only way to get past this problem, other than using one thread, was to let the unfinished jobs complete. The thread that acquired the lock on the SeaBIOS git repository would finish building SeaBIOS, so that target would not need to be remade. When restarting the build, only the target that failed is rebuilt, so it does not collide with any other thread. To address this issue, make the SeaVGABIOS file target depend directly on the SeaBIOS file instead, and remove the duplicate "seabios" target. Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02lz4: Fix out-of-bounds readsAlex Rebert
Fix two out-of-bounds reads in lz4 decompression: 1) LZ4_decompress_generic could read one byte past the input buffer when decoding variable length literals due to a missing bounds check. This issue was resolved in libpayload, commonlib and cbfstool 2) ulz4fn could read up to 4 bytes past the input buffer when reading a lz4_block_header due to a missing bounds check. This issue was resolved in libpayload and commonlib. Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr}Alex Rebert
cbfs_get_handle() and cbfs_get_attr() are both looping over elements to find a particular one. Each element header contains the element's length, which is used to compute the next element's offset. Invalid or corrupted CBFS files could lead to infinite loops where the offset would remain constant across iterations, due to 0-length elements or integer overflows in the computation of the next offset. This patch makes both functions more robust by adding a check that ensure offsets are strictly monotonic. Instead of infinite looping, the functions are now printing an ERROR and returning a NULL value. Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-29payloads/tianocore: Enable PS2 keyboard moduleBenjamin Doron
Upstream UEFIPayload[1] now includes support for PS2 keyboards, but defaults it to disabled. Enable it, as CorebootPayload does. Note that this increases payload size in coreboot by a little over 5 KiB. 1. https://github.com/tianocore/edk2/commit/33a32936510ecff00d0b6aeaeb9c8b2bf5430b8b Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38960 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-28payloads/ext/tianocore/Makefile: Enable quiet modeAngel Pons
The build process of this payload is unnecessarily prolix. Therefore, make use of the `-q` flag to abridge the output. TEST=When building for X64, UEFIPAYLOAD.fd does not differ. Change-Id: I6eba069ff5be2813d180dae40ab10155f0542f33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39123 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24libpayload: cbgfx: Fix potential overflowing expressionYu-Ping Wu
BRANCH=none BUG=none TEST=none Change-Id: Icd37a6abc01d9fcbcf54525d47b15c9930a9b9fb Signed-off-by: Yu-Ping Wu <yupingso@google.com> Found-by: Coverity Scan #1419491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24libpayload: Fix out-of-bounds readAlex Rebert
Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Ie442f82cd1abcf7fa18295e782cccf26a7d30079 Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-22cbfs: allow uncompressed payloadsRonald G. Minnich
Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39051 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17payloads: Fix typosElyes HAOUAS
Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17libpayload/corebootfb: Fix character buffer relocationNico Huber
The `chars` pointer references the heap which is part of the payload and relocated along with it. So calling phys_to_virt() on it was always wrong; and the virt_to_phys() at its initialization was a no-op anyway, when the console was brought up before relocation. While we are at it, add a null-pointer check. Change-Id: Ic03150f0bcd14a6ec6bf514dffe2b9153d5a6d2a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-17libpayload: arm64: Keep instruction cache enabled at all timesJulius Werner
This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-05libpayload: Make pci and endian handling -Wconversion safePatrick Georgi
Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-02-05libpayload/xhci: Fix MPS handling in set_addressKangheui Won
We set MPS to speed_to_default_mps(speed) initially but later compare maxpacketsize with 8 to change mps. So compare with speed_to_default_mps(speed) to determine if we need to change settings here. BUG=b:147783572 BRANCH=none TEST=works with 12Mbps/8MPS USB device Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04coreinfo/coreinfo.c: Correct main function signatureJacob Garber
libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14libpayload: cbgfx: Support drawing a box with rounded cornersYu-Ping Wu
A function draw_rounded_box() is added to draw a box with rounded corners. In addition, this function is different from draw_box() in 2 ways: - The position and size arguments are relative to the canvas. - This function supports drawing only the border of a box (linear time complexity when the thickness is fixed). BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-27Makefile: Remove romccElyes HAOUAS
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-20libpayload/drivers/i8042: add error messages to i8042_probeEric Lai
Print error message before error return for better debugging. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/37689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-16libpayload: Implement reading from CBMEM consoleYu-Ping Wu
To support showing CBMEM logs on recovery screen, add a function cbmem_console_snapshot() to copy the CBMEM console to an allocated buffer. Non-printable characters are automatically replaced with '?' to ensure the returned string is printable. BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-13payloads/seabios: Update stable from 1.12.1 to 1.13.0Martin Kepplinger
SeaBIOS 1.13.0 has been tagged on 20191209. Major changes in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups see http://seabios.org/Releases Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-13libpayload/drivers/i8042: Add error handlingEric Lai
Add error handling on I8042_CMD_WR_CMD_BYTE failure. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-12libpayload/drivers/i8042: Remove obsolete flagEric Lai
CB:37594 change the flag makes PC_KEYBOARD_IGNORE_INIT_FAILURE obsolete. Remove it. BUG=b:145130110 TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcf816155b32dd691b48a7479297b556d32dd6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11libpayload/drivers/i8042: Add AT translated Keyboard supportEric Lai
Wilco device uses the AT translated keyboard and doesn't need to set scancode set. Remove the ignore flag and put into translation mode instead. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-09payloads/bayou: remove unhooked payloadAngel Pons
The bayou payload is not attached to the build system in any way, and has not been for quite a while. Since selecting it in Kconfig does nothing, remove this payload now that coreboot 4.10 has been released. Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06endian: Replace explicit byte swapping with compiler builtinJulius Werner
gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-05arm64: Bump exception stack size to 2KBJulius Werner
To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-05trogdor: libpayload USB supportT Michael Turney
Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04mmio: Add clrsetbitsXX() API in place of updateX()Julius Werner
This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot tableYu-Ping Wu
Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-28libpayload: Add BIT(x) macro definitionsatya priya
Add BIT(x) macro definition in libpayload. Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40 Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 20:25:03 +0000