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2020-11-22payloads/external/Makefile.inc: Fix SeaBIOS option regressionsAngel Pons
Commit 14ca7407196 (Makefile.inc: Move adding SeaBIOS cbfs config files) introduced various regressions that were not spotted during review. TEST=Building with SEABIOS_THREAD_OPTIONROMS is working properly again. Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47814 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16Makefile.inc: Move adding SeaBIOS cbfs config filesArthur Heymans
Using the INTERMEDIATE target this can be done in the proper dir. Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16libpayload/i8042: Increase response timeout to 1.5sNico Huber
The current timeout of 500ms is too low. For instance self-test of the KBC integrated into IT8516E took almost 1s in tests. We already check for presence of the KBC before the self-test. So the timeout should only trigger on a hardware defect and we can leave some margin. Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-12Delete mainboard/google/chezaJulius Werner
Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09libpayload: storage.c: remove unneeded #if CONFIG()Thomas Heijligen
Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08libpayload: Make OHCI enums into typesJacob Garber
The OHCI header file declares various enums as follows: enum { ... } enum_name; Since the name is at the end, this is actually declaring a variable called enum_name and *not* a type, which is causing a multiple definition error in GCC 10. Move the enum_name before the opening brace to prevent this. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08libpayload: Add compiler.h to compiler parametersJacob Garber
Headers in libpayload define various structs like so: struct struct_name { ... } __packed; However, these header files do not include the compiler.h macro that defines what __packed is, so they are actually defining a variable named __packed and *not* declaring a packed struct. This leads to defining the same variable multiple times, which was caught by GCC 10. Add compiler.h to the compiler parameters so it is included in all files automatically. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-02coreinfo: Add support for link time optimizationJacob Garber
This introduces a Kconfig option for compiling coreinfo with LTO. This option can be used independently of LTO in libpayload, though will benefit most if that is enabled as well. If both are enabled, the final size of coreinfo.elf is reduced from 95 KiB to 92 KiB. Tested in QEMU and on Thinkpad T500. Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38293 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02libpayload: Add support for link time optimizationJacob Garber
Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 114 KiB 11.49s LTO 95 KiB 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38291 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02libpayload/x86: Try to discover invariant TSC rateNico Huber
We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-02libpayload/x86: Add enumeration of Intel family 6 modelsNico Huber
The list is incomplete and only contains what we need in the follow-up commit. It can be extended at will. Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-30lib/libpayload: Replace strapping_ids with new board configuration entryTim Wawrzynczak
There are currently 3 different strapping ID entries in the coreboot table, which adds overhead. The new fw_config field is also desired in the coreboot table, which is another kind of strapping id. Therefore, this patch deprecates the 3 current strapping ID entries (board ID, RAM code, and SKU ID), and adds a new entry ("board_config") which provides board ID, RAM code, SKU ID, as well as FW_CONFIG together. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30.gitignore: Split into subdirectory filesPatrick Georgi
There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28payloads/filo: Set stable tag to something that buildsNico Huber
Also rename the prompt to "tested" to make it more obvious that there is no really stable version. Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-26libpayload/keyboard: Use `bool` as return typeNico Huber
Use `bool` whenever `0` was used to indicate an error. The mixing of different types for return values was mildly confusing and potentially dangerous with the i8042 API close by that uses `0` for success. Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26libpayload/curses: Use <stdbool.h>Nico Huber
Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26libpayload: Add <stdbool.h>Nico Huber
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph
SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-20libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()Felix Singer
Clean up ahci_initialize() by using pci_dev struct. Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/storage/ahci: Use pacc pointer to read device classFelix Singer
The PCI bus gets already scanned while gathering system information. Therefore, use the pacc pointer from sysinfo_t to read the device class of PCI devices instead of rescanning the bus. Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/arch/x86: Introduce pacc pointer in sysinfo_t structFelix Singer
Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20payloads/coreinfo: Rename pci_scan_bus()Felix Singer
Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19libpayload/storage: Enable STORAGE_64BIT_LBAFelix Singer
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB capacity. Therefore, enable the 64-bit support. Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19libpayload/storage: Enable all AHCI controllers by defaultFelix Singer
Since the list of tested controllers is not actively maintained, enable all AHCI controllers by default. Also, improve the readability of its help text by adding a comma to it. Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-17libpayload/libpci: Introduce device class attribute in pci_devFelix Singer
The device class is read at different places and it is read from the hardware directly. Therefore, and in preparation to CB:46416, introduce the device class attribute in the pci_dev struct. With this, there is only one interaction with the hardware and it's also more user friendly. Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46347 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17libpayload/libpci: Clean up pci_alloc()Felix Singer
Clean up pci_alloc() and return pointer to allocated memory directly. Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-16libpayload/x86: Add some more CPUID helpersNico Huber
Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-15lib and libpayload: Add popcnt functionsAngel Pons
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers. Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14lib and libpayload: add 64-bit versions of clz, __ffs and log2Tim Wawrzynczak
Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`, and `log2_64`. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30libpayload: use PRIu64 type to print u64Jeremy Compostella
The appropriate way to print a u64 variable regardless of the current architecture is to use the PRI*64 macros. libpayload is mostly used in 32 bits but when ported to other projects and compiled in 64 bits it breaks the compilation. Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7633 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-09-27libpayload: Fix file permissionsKyösti Mälkki
Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26payloads/external: add support for BOOTBOOT payloadZoltan Baldaszti
BOOTBOOT is a multi-platform, architecture agnostic boot protocol. The protocol describes how to boot an ELF64 or PE32+ executable inside an initial ram disk image into clean 64 bit mode. This version uses libpayload to do that. Depending on the lib's configuration, initrd can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT partition or a file on a FAT formatted ESP partition. For more information see https://gitlab.com/bztsrc/bootboot Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0 Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21treewide/Kconfig: Drop unneeded empty linesElyes HAOUAS
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21payloads: Drop unneeded empty linesElyes HAOUAS
Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-19libpayload: free: Separate NULL check out for clarityHsuan Ting Chen
Separate the validity check of calling free(NULL) for clarity. BUG=b:168441735 TEST=emerge-puff libpayload Change-Id: I0dc355553410bbe59e658945fb40c05f5f709380 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18libpayload: cbgfx: Fix 'equals' counter for Lanczos resamplingYu-Ping Wu
The current initialization of the 'equals' counter is incorrect, so that when 'equals >= SSZ * SSZ', the pixels in the sample array might not be all the same, leading to a wrong pixel value being set in the framebuffer. The 'equals' counter stores the number of latest pixels that were exactly equal. Within the for loop of 'ox', the sample array is updated in a column-based order, and the 'equals' counter is updated accordingly. However, the 'equals' counter is initialized in a row-based order, which causes it to be set too large than it should be. Consider the example where sample[sx][sy] are initially: [X X X A A A] // sy = 0 [X X X B B B] [X X X B B B] [X X X B B B] [X X X B B B] [X X X B B B] // sy = SSZ Then, the correct implementation will initialize 'equals' to be 15, with last_equal being B. Suppose all of the remaining pixels are B. Then, at the end of the 'while (fpfloor(ixfp) > ix)' loop when ix = 4, or equivalently after 4 more columns of sample are updated, 'equals' will be 15 + 6 * 4 = 39, which is greater than SSZ * SSZ = 36, but we can see there are still 2 A's in the sample: [B B B B A A] [B B B B B B] [B B B B B B] [B B B B B B] [B B B B B B] [B B B B B B] Therefore, we must also initialize the 'equals' counter in a column-based order. BUG=b:167739127 TEST=emerge-puff libpayload TEST=Character 'k' is rendered correctly on puff BRANCH=zork Change-Id: Ibc91ad1af85adcf093eff40797cd54f32f57111d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-14coreinfo: Use SPDX license identifiersJacob Garber
- Remove copyright notices and add authors to AUTHORS - Use SPDX license identifiers for all files - Add coreinfo to the license header lint Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-13libpayload: malloc: Fix realloc for overlapping buffersYu-Ping Wu
The current realloc() works by freeing the origin buffer, allocating a new one, and copying the data over. It's true that free() won't touch the actual memory. However, the alloc() following it will potentially modify the memory that belongs to the old buffer in order to create a new free block (right after the newly allocated block). This causes 8 bytes (HDRSIZE) to be overwritten before being copied to the new buffer. To fix the problem, we must create the header of the new free block after the data is copied. In this patch, the content of alloc() is split into two functions: 1. find_free_block(): Find a free block with large enough size, without touching the memory 2. use_block(): Update the header of the newly allocated block, and create the header of the new free block right after it Then, inside realloc(), call memmove() call right after find_free_block() while before use_block(). BUG=b:165439970 TEST=emerge-puff libpayload TEST=Puff boots TEST=Verified realloc() correctly copied data when buffers overlapped Change-Id: I9418320a26820909144890300ddfb09ec2570f43 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-04libpayload/xhci: Fix Slot State field width definitionCaveh Jalali
According to the xHCI spec, the Slot State field in the Slot Context Data Structure is 5 bits wide. So, fix the code to match. ref. xHCI spec 1.2 section 6.2.2, Figure 6-2: Slot Context Data Structure BUG=none TEST=xHCI compiles Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45023 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31xhci: Do not set the CRCR_CS bitCaveh Jalali
We do not need to set the CS (Command Stop) bit in the Command Ring Control Register. CS is implied by CA (Command Abort). I'm not sure if there is a defined execution order for these command bits, so it's safer to only use the CA bit as it includes the CS function. Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24. BUG=b:160354585,b:157123390 TEST=able to boot into recovery using USB stick on servo v2 on volteer as well as HooToo 8-1 hub Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-31xhci: Fix Abort command event handlingCaveh Jalali
This fixes issues with how we handle events generated by the xHCI "command abort" command. first, depending on the state of the xHCI controller, the COMMAND_ABORTED may not be generated. If the controller was between commands, only the COMMAND_RING_STOPPED event will be generated. Second, do not adjust the command ring "cur" pointer as that just confuses the controller. BUG=b:160354585,b:157123390 TEST=able to boot into recovery using USB stick on servo v2 on volteer as well as HooToo 8-1 hub Change-Id: I055df680d1797f35d9730e2bfdb4119925657168 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-28libpayload: cbgfx: Support buffered I/OHung-Te Lin
For payloads with UI based on CBGFX, they usually start by calling clear_canvas or clear_screen and then draw the UI elements. However, that makes the screen flicker. A typical solution is to identify and minimize the area to redraw. However for payloads with complicated UI and do not care about latency, an alternative is to enable buffered I/O. The new enable_graphics_buffer() will redirect all graphics I/O into an invisible working buffer. To flush (redraw) the buffer to the real screen, call flush_graphics_buffer(). To stop buffering, call disable_graphics_buffer(). BUG=None TEST=Add the enable, flush and disable calls to payload 'depthcharge', built a firmware and boots into Chrome OS recover UI. No more flickering. The average rendering time on x86 platform is 1.2ms. Change-Id: Id60a2824fd9e164feae16b92b68b003beabea8d3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44654 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24libpayload: memmove: Don't make expectations of architecture memcpyJulius Werner
default_memmove() calls memcpy() when (src > dst). This is safe for the default_memcpy() implementation, but just calling memcpy() may invoke an architecture-specific implementation. Architectures are free to implement memcpy() however they want and may assume that buffers don't overlap in either direction. So while this happens to work for all current architecture implementations of memcpy(), it's safer not to rely on that and only rely on the known implementation of default_memcpy() for the forwards-overlapping case. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7ece4ce9e6622a36612bfade3deb62f351877789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24libpayload: Cache physical location of stringsNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates the remaining pointers that are not consumed by libpayload code, all of them strings. Also update the comment that `libsysinfo` only containts physical addresses. Change-Id: I9d095c826b00d621201c34b329fb9b5beb1ec794 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of CBMEM entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to CBMEM entries that are not consumed inside libpayload code. Change-Id: I3be64c8be8b46d00b457eafd7f80a8ed8e604030 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24libpayload: Cache physical location of cb_table entriesNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to coreboot-table entries that are not consumed inside libpayload code. Change-Id: I95cb0af151e0707a1656deacddb8a5253ea38fc3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache copy of `cb_framebuffer` structNico Huber
Our AArch64 code supports dynamic framebuffer allocation which makes it necessary to change the framebuffer information during runtime. Having a pointer inside `libsysinfo` made a mess of it as the pointer would either refer to the original struct inside the coreboot table or to a new struct inside payload space. The latter would be unaffected by a relocation of the payload. Instead of the pointer, we'll always keep a copy of the whole struct, which can be altered on demand without affecting the coreboot table. To align the `video/graphics` driver with the console driver, we also replace `fbaddr` with a macro `FB` that calls phys_to_virt(). Change-Id: I3edc09cdb502a71516c1ee71457c1f8dcd01c119 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical location of serial-console structNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: Icd30e95c6b8115d16dd793914fb01a1a9da1854f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical CMOS option table locationNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: I64a37bef263022edb504086c02a3fd22ce068ba4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24libpayload: Cache physical cbmem console addressNico Huber
Same as with other consoles and drivers that cache an address outside the payload (e.g. video/corebootfb), we should store the physical address, so we can derive the virtual address on demand. This makes it save to use the address across relocations. As a first step in migrating `libsysinfo` to `uintptr_t`, we also switch to the physical address there. Fixes the default build of FILO, tested with Qemu/i440FX and Qemu/Q35. Change-Id: I4b8434af69e0526f78523ae61981a15abb1295b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 04:24:02 +0000