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2016-03-05BuildSystem: Add Memtest86+ as a secondary payloadMartin Roth
This allows memtest86+ to be added to CBFS as a 'secondary' payload on x86 systems, to be loaded by the main payload if desired. Selecting this option, which defaults to no, builds the memtest86+ payload and adds it to CBFS as `img/memtest` which can then be loaded by for example SeaBIOS or GRUB. Change-Id: Iecf876aaf588ba1df7abdf6668cb26f089bf5f42 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13858 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-02-28coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC)Iru Cai
Without this change it'll get a build error with crossgcc-x64 because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32", and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of "x86_64-elf-as". Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/13845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-26payloads: Load coreinfo as a secondary payloadMartin Roth
This allows coreinfo to be added to CBFS as a 'secondary' payload on x86 systems, to be loaded by the main payload if desired. Selecting this option, which defaults to no, builds the coreinfo payload and adds it to CBFS as `img/coreinfo` which can then be loaded by for example SeaBIOS or GRUB. Change-Id: I52661d486823bc4bb215ce92dca118c9d2c2a309 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13728 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-26nvramcui: Add MakefileDenis 'GNUtoo' Carikli
Users had to build nvramcui manually because payload.sh was only meant for abuild. Now the user can build it with: cd payloads/libpayload/ && make menuconfig && make && make install cd ../nvramcui && make Change-Id: I409a3c39a1e1738e8071febb1a3f169e1aee959a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13778 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-24u-boot: Make sure targets aren't duplicatedMartin Roth
When U-Boot isn't selected as a payload, two of the targets: $(project_dir): and $(project_dir)/$(TAG-y) evaluated to the same value, generating a make warning when running a clean. By adding additional text to the file that is created, this is avoided. Gets rid of these warnings: Makefile.inc:54: warning: overriding commands for target `u-boot' Makefile.inc:37: warning: ignoring old commands for target `u-boot' Change-Id: I4b4df753612b674b3ccde2a757338840be92d1f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22cbfs: Add LZ4 in-place decompression support for pre-RAM stagesJulius Werner
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-19libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSCAaron Durbin
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information exported in the coreboot tables as the cpu_khz frequency. That allows get_cpu_speed() not to be called which currently relies on the 8254 PIT. As certain x86 platforms allow that device to be optional or turned off for power saving reasons, allow a path where get_cpu_speed() is no longer called. Additionally, this approach also allows the libpayload to not duplicate logic that already exists in coreboot. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed in payload TSC frequency is honored instead of using get_cpu_speed(). Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13671 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-18Payloads: Add U-Boot as a coreboot-payloadMartin Roth
- Add Kconfig and Makefile options to use U-Boot as a payload. - Add Kconfig option for extra cbfstool command line arguments. - Add Kconfig & Makefile option to load the payload as a flat binary. - Add u-boot directory to .gitignore. This is currently working for X-86 only. Graphics worked in U-Boot correctly by initializing the VBIOS and setting up a console mode. Tested in QEMU and on Minnowboard Max. Got into U-Boot, have not booted an OS yet. Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/12714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-17payloads/external/GRUB2: Add a possibility to add custom modules.Vladimir Serbinenko
Change-Id: I3004eac248561b0cd4e44bcef90fc66fae5d77ca Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13727 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-02-09SeaBIOS: Disable serial console if serial is memory mappedMartin Roth
SeaBIOS only supports standard IO based serial ports. If the serial port being used by coreboot isn't a standard IO serial port, disable the serial console in the SeaBIOS build. Change-Id: I386b46625fca0bd0a5416ed9831f8370c294ed74 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13617 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09libpayload: use 32bit access when accessing 4byte wide uart registersPatrick Georgi
This fixes serial on rk3288. Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13636 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-09Kconfig: Move payloads section to payloads/KconfigMartin Roth
Move the payloads section of the kconfig tree out of the top level kconfig file and into a separate Kconfig just for payloads before it starts to get added to. Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-04libpayload: Add timer driver for armada38xRuilin Hao
Add timer driver for armada38x BUG=chrome-os-partner:47462 TEST=emerge-cyclone libpayload BRANCH=tot Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635 Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313343 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02payloads/coreinfo: Add defaultbuild targetMartin Roth
Add a single target to do the full coreinfo build using default Kconfig values for both coreinfo and libpayload. Change-Id: Id622fb2df480e826f6d868dbe01385d76587be26 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18payloads: fix dependencies for seabios and filoPatrick Georgi
config and revision data need to be around before they're added to CBFS. Change-Id: I195156773effd5137c3fda3639c002fbec6e7158 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14cbgfx: add error code to cbgfx_initDaisuke Nojiri
cbgfx_init can fail for multiple reasons. These codes help debugging cbgfx_init. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315550 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-20Makefile.inc: Move addition of payload rev & config to payload makefileMartin Roth
These files need to be added to cbfs-files after PAYLOAD_CONFIG and PAYLOAD_VERSION have been defined. Where they were before, they didn't get added to the final build. Change-Id: Ib1b230f9eb72a8c1710ef473a9f24c0fb7ec6e17 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16libpayload: add archive.hDaisuke Nojiri
archive.h is a header file for the programs which need to parse an archive created by 'archive' tool. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311201 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/12734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.veyron: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06libpayload/configs/config.purin: Use CONFIG_LP_8250_SERIAL_CONSOLEMartin Roth
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE. - CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the default values for these new config options. CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver) Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06SeaBIOS: remove VERSION variable in coreboot MakefileAlexander Couzens
SeaBIOS dropped support of VERSION variable and is reproducible without it. Change-Id: Iea1dc20e18aa5c274060e3cd55cd9e95086a602d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12645 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2015-12-05build system: add dependencies for GRUB2 and FILOPatrick Georgi
Make sure the build system knows how to start building the various integrated payloads we support. Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12641 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-05build system: Drop useless variable and dependencyPatrick Georgi
We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't need to be an explicit dependency. Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12648 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-04external/Makefile.inc: Update SeaBIOS version fileMartin Roth
SeaBIOS updated how versioning is done, and out/version.c no longer exists. The new file with version information is autoversion.h. Change-Id: I10abee73ecc51e52c9ff7a2e7a9099339b1a4b40 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12567 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-04SeaBIOS: update stable release from 1.8.2 to 1.9.0Alexander Couzens
* The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12566 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY optionMartin Roth
This has been replaced by the PAYLOAD_CONFIGFILE option, allowing any SeaBIOS config option to be set by a platform. Change-Id: I584c4c481266740840158baba76581d68e69b448 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12570 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03payloads/external/SeaBIOS: Add option for saved SeaBIOS .configMartin Roth
Instead of adding various SeaBIOS options into the coreboot Kconfig, just add a way to use saved SeaBIOS .config files. These files can contain full SeaBIOS .configs, but is really intended for individual options. The coreboot Kconfig options take precedence over the settings in the saved .config. Change-Id: Ia7f9c76555b8e290777207b3f637c94c4d67a782 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12568 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03libpayload: get cbfs offset & size for default media from lib_sysinfoDaisuke Nojiri
This change revives the path which was made inert by CL:308520. When media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer to a default media. Thus, get_cbfs_range does not set cbfs offset & size from lib_sysinfo. BUG=chrome-os-partner:47772 BRANCH=tot TEST=Tested on Jerry and Glados Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89 Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02coreinfo: use coreboot crosscompilerMartin Roth
Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross compiler toolchain. Restrict to x86_32 gcc compiler. Tested in QEMU Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12454 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-30build system: add dependencies for SeaBIOS outputPatrick Georgi
Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12577 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-28libpayload: Remove redundant 8250 MMIO32 UART driverAlexandru Gagniuc
The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-21coreinfo: Rewrite bootlog_moduleYasha Cherikovsky
The old bootlog_module implementation was completely broken: - It assumed that the console buffer is located at address 0x90000, and of size 64K. It is not correct nowadays. - It displayed the buffer in a very hacky way, the code was riddled with TODOs and FIXMEs. Scrolling had sometimes unexpected behavior. The new implementation: - Uses the cbmem console as the source of data. It takes the console information from lib_sysinfo of libpayload, which is constructed from the coreboot tables (no more hardcoded adressess). - Properly sanitizes the console buffer for display, which makes scolling and display much easier to implement. Change-Id: I3f87ec920631da2acfd3f52273228703f22f469f Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com> Reviewed-on: http://review.coreboot.org/12440 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20libpayload: PDCurses: Remove trailing whitespaceStefan Reinauer
find . -type f |xargs perl -pi -e 's, *$,,' find . -type f |xargs perl -pi -e 's, *$,,' Change-Id: I62c2bc15b7c395a68b68422e701edf98b08e27c6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-19coreinfo: Move screen dimensions to headerYasha Cherikovsky
The screen dimensions need to be known in other files. Change-Id: Idf6f02e4cadbece78096ccd464296ecec405574d Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com> Reviewed-on: http://review.coreboot.org/12439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19coreinfo: Fix off-by-one in displayed month of yearYasha Cherikovsky
According to C documentation, the range of tm_mon in struct tm is [0, 11]. Before the patch, the displayed month was indeed incorrect. Change-Id: I9f95f1e978c45b3635e2edfe1ec496d7b0dec00a Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com> Reviewed-on: http://review.coreboot.org/12438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19coreinfo: Hide blinking cursorYasha Cherikovsky
Change-Id: I6297fc178203dcfbd0b2a4c78dd83359e7804933 Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com> Reviewed-on: http://review.coreboot.org/12437 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-13libpayload: udc/dwc2: Ignore setup packet in check for queue emptyFurquan Shaikh
during shutdown DWC2 UDC controller always requires an active packet to be present in EP0-OUT to ensure proper operation of control plane. Thus, during shutdown ignore EP0-OUT for queue empty check if only 1 packet is present. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. "fastboot reboot-bootloader" reboots device without timeout in udc shutdown. Change-Id: Iafe46c80f58c4cd57f8d58f060d805b603506bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4e7c27d849c0411aae58e60a24d8170a27ab8485 Original-Change-Id: Ifa493ce0e41964ee7ca8bb3a1f4bb8726fa11173 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311257 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12413 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-13libpayload: queue: Add a helper macro for checking singleton queueFurquan Shaikh
Check if the simple queue consists of only 1 element. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0 Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311256 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12412 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-11libpayload: Rename PDCurses-3.4 to PDCursesStefan Reinauer
Change-Id: If881ec130833c7e7e62caa3d31e350a531f5bc8e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11PDCurses: Don't hard code version numberStefan Reinauer
Don't hard code the PDCurses version number in every file added to the object list. Change-Id: Ic2e9230b7e3089c60dd7f442e3ea7baffb4aa400 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12397 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10libpayload/udc: dwc2: Add handler for add_stringsFurquan Shaikh
BUG=b:24676003 BRANCH=None TEST=Compiles successfully. fastboot devices shows serial number for shark. Change-Id: I61d6c168fa458d1f880bc566db997aa5d6398361 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 45b286b318281aea9a4b0362c9259d748b66fd28 Original-Change-Id: Ib9cc22de9daa6c5ec9cde1e62c6f5f768e946069 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310984 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10libpayload/udc: dwc2: Add timeout for shutdown operationFurquan Shaikh
BUG=b:24676003 BRANCH=None TEST=Verified that udc shutdown returns after the timeout. Change-Id: I5df598c4eddecbecb353343ef5a4e44eae4fc20b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 268913f21adea9969c9f88e3cb759341a60719f0 Original-Change-Id: I3ee059791d6e821f83f9ac41fd7c5385bd60e21e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310983 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12347 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-05libpayload: xhci: Add delay to get reset working more reliablyRajmohan Mani
Existing Intel xHCI controllers require a delay of 1 ms, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12325 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05libpayload: Avoid confusing usb debug output in dwc2 driverPatrick Georgi
enqueue_packet already runs start_ep_transfer, which enqueues the next job. It's pretty much guaranteed that the port will look busy. BUG=none BRANCH=none TEST=no spurious ep 0-0 busy messages Change-Id: I9cbfa7b51dd37564262295ddbcdd0755da40c05b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8997dbd78dc363334f4e22eaa61f25de1449ffba Original-Change-Id: I8a39713fc1d6f16b80284e0f21dc95685716a9b7 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308763 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: yunzhi li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/12259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05libpayload: Fix building dwc2 UDC driver with debug enabledPatrick Georgi
hexdump() now takes a pointer instead of an int-containing-an-address. BUG=none BRANCH=none TEST=building with USB_DEBUG works Change-Id: Idd0c43031a212c8f3b6489f533c488805d98d6a9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8660f6091bb124eeabe73302e8c7f1a8e46324f1 Original-Change-Id: I266efcb8b939d6da104ad05a3e79a78065c60beb Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308762 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: yunzhi li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/12258 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05libpayload: Allow non-default CBFS mediaPatrick Georgi
CBFS requests were always fulfilled using the CBFS specified in cbtables. That's a great policy when default requests are sought, but not so great when the user deliberately asked for something else. So check if they want default CBFS media information, otherwise ignore cbtables data. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I01b63049eebfba6f467808ac84ef77385840c204 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621c916ab14c0de4bae3dde09c05060c4f3c63c5 Original-Change-Id: Ia4a8848fd7db9d9a2bf9f5c226566fe3936ff543 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308520 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29libpayload: usbmsc: Add small delay during initialization to fix CZ60Julius Werner
We found that some SanDisk Cruizer Glide CZ60 sticks (confirmed on 16GB and 64GB versions) have a problem responding to our first GET_MAX_LUNS request right after they received their SET_CONFIGURATION. They will continually return a NAK until the host gives up (which is 2 user-noticable seconds for us). Adding a small delay of about 15us seems to be enough to fix the issue, but let's do 50 to be save. Confirmed with both MT8173 and Intel LynxPoint XHCI controllers. BRANCH=None BUG=chrome-os-partner:45473 TEST=No notable delay before detecting stick on Oak and Falco. Change-Id: Ib03944d6484de0ccecbb9922d22666f54c9d53dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 589f19a901275fb8b00de4595763a7d577bed524 Original-Change-Id: I95c79fe40d3ad79f37ce2eb586836e5de55be454 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308980 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29libpayload: Fix building dwc2 UDC driverPatrick Georgi
Change Ie54699162 changed a structure's name and field names and we didn't notice. Adapt. BUG=none BRANCH=none TEST=building with UDC_DWC2 works Change-Id: I592ebc29b2a08a23e6dbc9d2186807cbbbbca330 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3dda8ad5ffc36593d8b8fd6664a7f9b4816f0f93 Original-Change-Id: I4a065de0f4045a01bef1dc9fbb2e0578b5508518 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308791 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12228 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-28cbfs: read cbfs offset and size from sysinfoDaisuke Nojiri
This change allows libpayload to read cbfs offset and size from sysinfo. Legacy way of locating cbfs reagion is still supported in case sysinfo doesn't store the offset and the size. BUG=none BRANCH=master TEST=tested on samus and smaug Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296993 Original-Commit-Ready: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11557 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 16:38:22 +0000