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2016-01-22Kconfig: Recommend not enabling UPDATE_IMAGE optionMartin Roth
We just had a user who spent a fair amount of time debugging a failing build due to this option being enabled. Add a little guidance that it probably shouldn't be enabled in the help text. Change-Id: I9339e442876c1fcd18ea564041c6cc1201c18ae5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22build system: Add option for auto generated cbfs attributesWerner Zeh
Add a new Kconfig variable to enable the generation of position and alignment attributes for cbfs files which has constraints on this parameters. In addition, modify Makefile.inc to support that option. Change-Id: Ibd725fe69a4de35964bdb2dde106d9a7c37ffb47 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22src/Kconfig: Indent with tabs instead of spacesMartin Roth
Change-Id: I47776d842b8d684fc11ac448b751892ee2bc5ecc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21Kconfig: add comments for toolchain choicesMartin Roth
- While we're working on fixing clang for coreboot, mark it as not currently working so that it doesn't look like a reasonable choice. - Add help on how to make the toolchains Change-Id: Ib37093ca98d0328fad40dd7886c98d00f78bd58e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13053 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21console: Simplify bootblock console Kconfig selection logicAlexandru Gagniuc
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures, allow the arch or platform to specify whether it can provide a C environment. This simplifies the selection logic. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-15lib: NHLT ACPI table supportAaron Durbin
Intel's SST (Smart Sound Technology) employs audio support which may not consist of HDA. In order to define the topology of the audio devices (mics, amps, codecs) connected to the platform a NHLT specification was created to pass this information from the firmware to the OS/userland. BUG=chrome-os-partner:44481 BRANCH=None TEST=Tested on glados. Audio does get emitted and some mic recording works. Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c Original-Change-Id: If469f99ed1a958364101078263afb27761236421 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12935 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
When microcode updates are enabled, this fixes an issue identical to that described in GIT hash 7b22d84d: * drivers/pc80: Add optional spinlock for nvram CBFS access Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12063 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30Kconfig: move fmap description file prompt into the mainboard menuMartin Roth
The FMD is board-specific, so it makes sense to have it in the mainboard menu. Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/12805 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit
Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11305 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17Kconfig: Fix CONFIG_GDB_STUB dependenciesDenis 'GNUtoo' Carikli
If we select CONFIG_GDB_STUB without CONFIG_SERIAL: build/console/console.romstage.o: In function `__gdb_hw_init': [...]src/include/console/uart.h:74: undefined reference to `uart_init' build/console/console.romstage.o: In function `__gdb_tx_byte': [...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte' build/console/console.romstage.o: In function `__gdb_tx_flush': [...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush' build/console/console.romstage.o: In function `__gdb_rx_byte': [...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte' Note that CONFIG_GDB_STUB should also work trough usbdebug, But due to the lack of testing, it has been disabled when added. This commit gives more information on the issue: f2f7f03 console: Add console for GDB Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-11build system: Switch to fmap based firmware layoutPatrick Georgi
We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/11692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-23IASL: Enable warnings as errorsMartin Roth
We've actually got more warnings now than when I first tested IASL warnings as errors. Because of this, I'm adding it with the option to have it disabled, in hopes that things won't get any worse as we work on fixing the IASL warnings that are currently in the codebase. - Enable IASL warnings as errors - Disable warnings as errors in mainboards that currently have warnings. - Print a really obnoxious message on those platforms when they build. ***** WARNING: IASL warnings as errors is disabled! ***** ***** Please fix the ASL for this platform. ***** Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-18Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGIONMartin Roth
HAS_PRECBMEM_TIMESTAMP_REGION was dependent on COLLECT_TIMESTAMPS, but should be allowed to be selected independently. My thought is that the code may only be used when collecting timestamps, the HAS prefix signifies that this is a platform configuration option. This fix could also be done by adding 'if COLLECT_TIMESTAMPS' everywhere that 'select HAS_PRECBMEM_TIMESTAMP_REGION' is used Change-Id: Iaf4895475c38a855a048dc9b82d4c97e5e3f4e5c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11338 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18Kconfig: fix typo in description of the TRACE optionBen Gardner
Change-Id: Icec6d047530e64228a3e71a636af4266ed5a73f0 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12457 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16arm64: Implement generic stage transitions for non-Tegra SoCsJulius Werner
The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-03drivers/pc80: Rework normal / fallback selector codeTimothy Pearson
Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-25Separate bootsplash image menuconfig option from othersKonstantin Aladyshev
The possibility of adding a bootsplash image to ROM should be independent from VGA_ROM_RUN and VESA menuconfig options. For example, the stored image could be saved in CBFS not for coreboot but for later use in SeaBIOS. Change-Id: I3a0ed53489c40d4d44bd4ebc358ae6667e6c797f Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/12129 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-20Enable MULTIPLE_CBFS_INSTANCES on x86, tooPatrick Georgi
It works there, we want it, disable that restriction. Change-Id: Idc023775f0750c980c989bff10486550e4ad1374 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/12094 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11Kconfig: Hide RAM_CODE_SUPPORT.Vladimir Serbinenko
It builds only on veyron_* which already select it, no need to ask user. Change-Id: Ie508b9eade16e0f39073b23dc0da6b6d1e0a4c73 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10380 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-10-11Kconfig: Hide BOARD_ID_MANUAL.Vladimir Serbinenko
board_id() returns an integer which is platform-specific. 0 for one port is different from 0 for another port. So there is no default board_id() and hence enabling it on boards other than urara would cause build failure. Not enabling it on urara or just setting id to "(none)" as is default results in board_id() = 0 which means urara and an error message on console. Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10379 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-08-30Kconfig: Remove EXPERT modeAlexandru Gagniuc
After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-08-13skylake: remove CBFS_SIZE option in SoC directoryAaron Durbin
CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. Remove from the soc Kconfig and add a default Kconfig for SOC_INTEL_SKYLAKE. BUG=chrome-os-partner:43419 BRANCH=None TEST=built glados Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289833 Original-Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11168 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-14riscv-emulation: Set stack size to 0 in KconfigThaminda Edirisooriya
Build now decides the stack size by correctly referencing the value in /src/mainboard/emulation/qemu-riscv/memlayout.ld. Note that while the size is correct, the placement is still wrong, and causes the stack to be corrupted by the coreboot tables. Still needs to be addressed Change-Id: I86c08bd53eeb64e672fecba21e06220694a4c3dd Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/10870 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-07payloads: Reorganize Kconfig for external payloadsStefan Reinauer
The integration of external payloads in coreboot is a bit messy. You have to change the to level Kconfig file for every payload (something that we recently fixed for mainboards and chipsets). This means that updating e.g. the SeaBIOS version requires a change outside of the SeaBIOS directory. With this patch you can create a new directory under payloads/external and place a Kconfig and Kconfig.name file in there, and the payload will automatically show up when you do "make menuconfig". Change-Id: I293abcb8eae581d4b3934e64897c0d339a27e7c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07timestamp: add generic cache regionAaron Durbin
In order to accommodate tracking timestamps in all the __PRE_RAM__ stages (bootblock, verstage, romstage, etc) of a platform one needs to provide a way to specify a persistent region of SRAM or cache-as-ram to store the timestamps until cbmem comes online. Provide that infrastructure. Based on original patches from chromium.org: Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223348 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10790 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-02Move baytrail & fsp_baytrail to the common IFD interface.Martin Roth
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23southbridge/intel: Create common IFD Kconfig and MakefileMartin Roth
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23Kconfig: Move CBFS_SIZE into Mainboard menuMartin Roth
The CBFS size is really mainboard specific, since it really depends on size of the chip on the mainboard, so it makes sense to have it in the mainboard menu along with the ROM-chip size. - Move the CBFS_SIZE definition up in src/kconfig - Move the Mainboard Menu markers out of src/mainboard/kconfig into src/Kconfig so CBFS_SIZE can live in the mainboard menu. - Add a long list setting default values to do what the chipset directories were previously defaulting the values to. This will be trimmed down in a following patch that creates a common set of IFD routines. (Who knew that kconfig supported line wrapping?) - Update the help text. Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10610 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-21Reorder arch & vendorcode in KconfigMartin Roth
Because Kconfig uses the first valid default that it comes across, the 'source' commands to load sub-Kconfigs should be ordered from the most specific (mainboards) to less specific (chipsets) to least specific (architectures). This allows the mainboards to override chipsets and architecture Kconfig files. Because the architecture files were getting loaded ahead of the chipset and cpu Kconfigs, the preferred defaults values for things such as NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set. Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10609 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-06-11lenovo: Hide SMBIOS configVladimir Serbinenko
It's derived from EEPROM on Lenovo machines and not from user config which is ignored. Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7055 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-06-10kconfig: Reorder config includesDuncan Laurie
The default ordering for the base kconfig entries has the CPU directory coming before the SOC directory, which means that the values in the CPU Kconfig take precedence. The first visible consequence of this is that CONFIG_SMM_TSEG_SIZE will be set to 0 on all SOC implementations. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: Ifd56a2ceb73ab335a86126e48d35ff4c749990ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0cddae37d3de1cbf3dd6afcf4a0707b7af9436fa Original-Change-Id: I98e3bf249650b50667dde62b6be9c1bf587ad0b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/276189 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10478 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-07acpi/sata: add generic sata ssdt port generatorAlexander Couzens
generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9708 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-06-02Kconfig: Remove RELOCATABLE_MODULES.Vladimir Serbinenko
RELOCATABLE_MODULES controls inclusion of rmodule support but including it without having anything that uses it is a pure waste of space. So instead make RELOCATABLE_MODULES be selected exactly when there is something using it. Change-Id: I377a955f0cd95b0f811b986df287864c3dc9f89a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26ACPI: slic supportVladimir Serbinenko
Export SLIC table from file in CBFS. Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7202 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-08fmaptool: Introduce the fmd ("flashmap descriptor") language and compilerSol Boucher
This adds a compiler for a language whose textual representation of flashmap regions will be used to describe the layout of flash chips that contain more than just a single CBFS. Direct integration with cbfstool (via a new command-line switch for the create action) is forthcoming but will be added separately. BUG=chromium:461875 TEST=Use Chromium OS's cros_bundle_firmware script on the fmap.dts file for panther. Using the latter file as a reference, write a corresponding fmap.fmd file and feed it through fmaptool. Run both binary output files though the flashmap project's own flashmap_decode utility. Observe only the expected differences. BRANCH=None Change-Id: I06b32d138dbef0a4e5ed43c81bd31c796fd5d669 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 005ab67eb594e21489cf31036aedaea87e0c7142 Original-Change-Id: Ia08f28688efdbbfc70c255916b8eb7eb0eb07fb2 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255031 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9942 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22rtc: add config flag to denote rtc API availabilityPatrick Georgi
RTC drivers now select RTC, so that code which depends on them can implement fallback behavior for systems that lack the hardware or driver. Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22build system: add manual board id supportStefan Reinauer
This patch adds manual board id support to coreboot and selects manual board ids vs automatic (ie strap based) where appropriate in the mainboards. CQ-DEPEND=CL:262935 BRANCH=none BUG=chrome-os-partner:37593 TEST=emerge-urara coreboot, see no board_id file emerge-buranku coreboot, see board_id file Change-Id: Ia04e5498a01f35c5418698ecaf3197f56415e789 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bdb1fa092005be24de9fc68998053982648da85 Original-Change-Id: I4f0820233a485bf92598a739b81be2076d4e6ae7 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262745 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Kconfig: Don't select GENERIC_GPIO_LIB in BOARD_ID_SUPPORTStefan Reinauer
The code guarded by BOARD_ID_SUPPORT does not use this library. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=emerge-storm coreboot succeeds in building an image. Change-Id: If8c5c326265441f0c10999e3882706432139fd89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f49b89e0b03f482a30dc652e5956494fb994cc70 Original-Change-Id: Ie2cd2cd049fdb20fa5cc368bee08babd3f7a551c Original-Reviewed-on: https://chromium-review.googlesource.com/262744 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>