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2018-08-10arm64: Turn architectural register accessors into inline functionsJulius Werner
Accesses to architectural registers should be really fast -- they're just registers, after all. In fact, the arm64 architecture uses them for some timing-senstive uses like the architectural timer. A read should be: one instruction, no data dependencies, done. However, our current coreboot framework wraps each of these accesses into a separate function. Suddenly you have to spill registers on a stack, make a function call, move your stack pointer, etc. When running without MMU this adds a significant enough delay to cause timing problems when bitbanging a UART on SDM845. This patch replaces all those existing functions with static inline definitions in the header so they will get reduced to a single instruction as they should be. Also use some macros to condense the code a little since they're all so regular, which should make it easier to add more in the future. This patch also expands all the data types to uint64_t since that's what the actual assembly instruction accesses, even if the register itself only has 32 bits (the others will be ignored by the processor and set to 0 on read). Arm regularly expands registers as they add new bit fields to them with newer iterations of the architecture anyway, so this just prepares us for the inevitable. Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Drop checks for current exception level, hardcode EL3 assumptionJulius Werner
When we first created the arm64 port, we weren't quite sure whether coreboot would always run in EL3 on all platforms. The AArch64 A.R.M. technically considers this exception level optional, but in practice all SoCs seem to support it. We have since accumulated a lot of code that already hardcodes an implicit or explicit assumption of executing in EL3 somewhere, so coreboot wouldn't work on a system that tries to enter it in EL1/2 right now anyway. However, some of our low level support libraries (in particular those for accessing architectural registers) still have provisions for running at different exception levels built-in, and often use switch statements over the current exception level to decide which register to access. This includes an unnecessarily large amount of code for what should be single-instruction operations and precludes further optimization via inlining. This patch removes any remaining code that dynamically depends on the current exception level and makes the assumption that coreboot executes at EL3 official. If this ever needs to change for a future platform, it would probably be cleaner to set the expected exception level in a Kconfig rather than always probing it at runtime. Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Remove set_cntfrq() functionJulius Werner
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30arm64: Add ARCH TimerT Michael Turney
SoC sdm845 uses ARCH Timer Change-Id: I45e2d4d2c16a2cded3df20d393d2b8820050ac80 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-02arch/arm: Correct checkpatch errorsLogan Carlson
Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-05-16arch/arm64: Use variables of the right size for msr/mrs opcodesPatrick Georgi
They do 64bit accesses, and gcc does the necessary fix ups to handle 32bit values as zero-padded 64bit values. clang, however, isn't happy with it. Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/19661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Rename Kconfig options for secmon and spintable to be prefixed with ARM64_ instead of ARCH_, which seems to be the standard throughout the rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this provides a clearer separation between generic options that are selected by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to some of the MAINBOARD_HAS_... we have) and options that only make sense in the context of a single architecture. Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: save and restore cntfrq for secondary cpusJimmy Huang
CNTFRQ_EL0 can only be set in highest implemented exception level. Save and restore CNTFRQ_EL0 for secondary cpus in coreboot. This patch fix the error below: SANITY CHECK: Unexpected variation in cntfrq. Boot CPU: 0x00000000c65d40, CPU1: 0x00000000000000 BRANCH=none BUG=none TEST=boot to kernel on oak board and check secondary cpu's cntfrq. confirmed cpu1's cntfrq is same as boot cpu's. Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c Original-Reviewed-on: https://chromium-review.googlesource.com/264914 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
TCR at EL1 is 64-bit whereas at EL2 and EL3 it is 32-bit. Thus, use 64-bit variables to read / write TCR at current EL. raw_read_tcr_elx will handle it automatically by accepting / returning 32-bit / 64-bit values. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I96312e62a67f482f4233c524ea4e22cbbb60941a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae71f87143f899383d8311a4ef908908116340d7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I459914808b69318157113504a3ee7cf6c5f4d8d1 Original-Reviewed-on: https://chromium-review.googlesource.com/231548 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9537 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07arm64: Add verstage supportFurquan Shaikh
This stage is not tested on any hardware. BUG=None BRANCH=None TEST=Compiles successfully for rush_ryu and veyron_pinky Original-Change-Id: I6dd266471c815895bb3dd53d34aacc8fe825eeb6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221911 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 907ea2d1f8c9f01d815e8673695dd5271322c7a8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I617a742d4a387be947086dae33e9a913f742a8d1 Reviewed-on: http://review.coreboot.org/9255 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions for writing sp_elxFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions with el argumentFurquan Shaikh
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25coreboot arm64: Add library for system accessFurquan Shaikh
Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d Reviewed-on: http://review.coreboot.org/8465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>