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path: root/src/arch/arm64
AgeCommit message (Expand)Author
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
2015-05-18arm64: psci: add cpu_suspend supportJoseph Lo
2015-05-11arm64: update verstage linkingAaron Durbin
2015-05-11cache: Add arch_program_segment_loaded call to arm and arm64Furquan Shaikh
2015-05-05arch/arm64: provide boot_cpu()Aaron Durbin
2015-04-30vboot: split class in library and stagePatrick Georgi
2015-04-28vboot2: Build verstage archive, then use that for building the stagePatrick Georgi
2015-04-27arch/arm64: update mmu translation table granule size, logic and macrosJimmy Huang
2015-04-27arm64: save/restore cptr_el3 and cpacr_el1 registersJoseph Lo
2015-04-27arm64: implement CPU power down sequence as per A57/A53/A72 TRMJoseph Lo
2015-04-27arm64: introduce data cache ops by set/way to the level specifiedJoseph Lo
2015-04-27arm64: perform early setup in secmon tooJoseph Lo
2015-04-27arm64: Allow cpu specific early setupFurquan Shaikh
2015-04-22armv8/secmon: Disable and Enable GIC in PSCI pathFurquan Shaikh
2015-04-22armv8/secmon: Correct PSCI function idsFurquan Shaikh
2015-04-22armv8/secmon: Correct names for SMC macrosFurquan Shaikh
2015-04-22arm64: save and restore cntfrq for secondary cpusJimmy Huang
2015-04-22arm64: add arm64_arch_timer_init functionJoseph Lo
2015-04-22arm64: Correct shareability option for normal memoryFurquan Shaikh
2015-04-22arch/arm64: allow floating-point registers accessYen Lin
2015-04-22arm64: provide icache_invalidate_all()Aaron Durbin
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
2015-04-21arm(64): Change write32() argument order to match x86Julius Werner
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
2015-04-14CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstoolJulius Werner
2015-04-10arm64: No need of invalidating cache line for secondary CPU stackFurquan Shaikh
2015-04-10arm64: Add support for save/restore registers for CPU startup.Furquan Shaikh
2015-04-10arm64: Add macro to invalidate stage 1 TLB entries at current ELFurquan Shaikh
2015-04-10arm64: Add conditional read/write from/to EL3 assembly macros.Furquan Shaikh
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
2015-04-10arm64: psci: actually inform SoC layer of CPU_ON entryAaron Durbin
2015-04-10arm64: ensure secondary CPU's stack tops are not in the cacheAaron Durbin
2015-04-10arm64: add timeout waiting for CPUs to come onlineAaron Durbin
2015-04-10arm64: Implement PSCI command supportAaron Durbin
2015-04-10arm64: secmon: add entry point for turned on CPUsAaron Durbin
2015-04-10arm64: secmon: pass online CPUs to secmonAaron Durbin
2015-04-10arm64: psci: use struct cpu_action to track startup entryAaron Durbin
2015-04-10arm64: secmon: prepare for passing more state into secmonAaron Durbin
2015-04-10arm64: secmon: wait for all CPUs to enter secmonAaron Durbin
2015-04-09arm64: secmon: direct non-BSP cpus to start before BSPAaron Durbin
2015-04-09arm64: psci: add node hierarchyAaron Durbin
2015-04-09arm64: add malloc support to secmonAaron Durbin
2015-04-09arm64: add mpidr field to cpu_info structAaron Durbin
2015-04-08arm64: Add timestamp.c to bootblock and verstageFurquan Shaikh
2015-04-07arm: Include types.h in clock.hPatrick Georgi
2015-04-07arm64: Add verstage supportFurquan Shaikh
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
2015-04-06build system: run linker scripts through the preprocessorPatrick Georgi
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