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2019-11-30arch/*/*/early_variables.h: drop unused filesArthur Heymans
Kill off NO_GLOBAL_MIGRATION finally! Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28arch/arm/include: Remove unused armv7 types.hJacob Garber
This header was originally copied from the Linux kernel. However, these days all fixed-width integers are defined in stdint.h, and all of the other typedefs in this file are kernel-specific and aren't used anywhere, so we can drop it. Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-10lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARGArthur Heymans
All targets now have the _cbmem_top_ptr symbol populated via calling arguments or in the nvidia/tegra210 case worked around by populating it with cbmem_top_chipset explicitly at the start of ramstage, so the Kconfig guarding this behavior can be removed. Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03arch/arm: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-09arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki
These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29arch/arm: Make ARM stages select ARCH_ARMArthur Heymans
This removes the need to select ARCH_ARM in SOC Kconfig Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26AUTHORS: Move src/arch/arm copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Make sure files say that they're part of the coreboot project - Move descriptions below the license header - Fix some spacing Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-12arch, include, soc: Use common stdint.hJacob Garber
There are only minimal differences between the architecture specific stdint.h implementations, so let's tidy them up and merge them together into a single file. In particular, - Use 'unsigned long' for uintptr_t. This was already the case for x86 and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64 used 'unsigned long long'. This change allows using a single integer type for uintptr_t across all architectures, and brings it into consistency with the rest of the code base, which generally uses 'unsigned long' for memory addresses anyway. This change required fixing several assumptions about integer types in the arm code. - Use _Bool as the boolean type. This is a specialized boolean type that was introduced in C99, and is preferrable over hacking booleans using integers. romcc sadly does not support _Bool, so for that we stick with the old uint8_t. - Drop the least and fast integer types. They aren't used anywhere in the code base and are an unnecessary maintenance burden. Using the standard fixed width types is essentially always better anyway. - Drop the UINT64_C() macro. It also isn't used anywhere and doesn't provide anything that a (uint64_t) cast doesn't. - Implement the rest of the MIN and MAX numerical limits. - Use static assertions to check that the integer widths are correct. Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21arch: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h' Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21arch/arm/cpu: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Id0e281ece0a647721c18402029cd6980f75d5908 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Separate MMIO and PNP opsKyösti Mälkki
Change-Id: Ie32f1d43168c277be46cdbd7fbfa2445d9899689 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-04src: Move {pci,pnp}_devfn_t to common 'device/pci_type.h'Elyes HAOUAS
Definitions of these types are arch-agnostic. Shared device subsystem files cannot include arch/pci_ops.h for ARM and arch/io.h for x86. Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-04src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30047 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24arch/arm/memmove.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-19arch/arm/include/armv7/arch: Remove dead codeElyes HAOUAS
Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-08-09src/arch: Fix typoElyes HAOUAS
Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14arch/arm/armv7: Fix coding styleElyes HAOUAS
Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-14pci: Fix compilation on non x86Patrick Rudolph
* Introduce pci_devfn_t on all arch * Add PCI function prototypes in arch/pci_ops.h * Remove unused pci_config_default() Change-Id: I71d6f82367e907732944ac5dfaabfa77181c5f20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25723 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04lib/bootmem: Add more bootmem tagsPatrick Rudolph
Introduce new bootmem tags to allow more fine grained control over buffer allocation on various platforms. The new tags are: BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that should not be touched by bootmem (by example: stack, TTB, program, ...). BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should not be touched by bootmem. Starting with this commit all bootmem methods will no longer see memory that is used by coreboot as usable RAM. Bootmem changes: * Introduce a weak function to add platform specific memranges. * Mark memory allocated by bootmem as BM_TAG_PAYLOAD. * Assert on failures. * Add _stack and _program as BM_MEM_RAMSTAGE. ARMv7 and ARMv8 specific changes: * Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE. ARMv7 specific changes: * Add _ttb_subtables as BM_MEM_RAMSTAGE. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21arch/arm/armv7: Correct checkpatch errorsLogan Carlson
- Correct whitespace issues with files under arch/arm/armv7. - Fix comments and remove unnecessary line continuations in mmu.c Change-Id: I69d50030b07b1919555feca44967472922176a81 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-07arch/*: Update Kconfig symbol usageMartin Roth
- Update all symbols to use IS_ENABLED() - Update non-romcc usage to use 'if' instead of '#if' where it makes sense. Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20005 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02arch/arm/include/armv7/arch: Correct keyword organization in cpu.hLogan Carlson
Move the inline keyword in between the static keyword and the return type. Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02arch/arm: Correct checkpatch errorsLogan Carlson
Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-12src/arch: Improve code formattingElyes HAOUAS
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15335 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28src/arch: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16287 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: Ibec78b25c0f330fc8517654761803e8abf203060 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16282 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 08:39:04 +0000