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path: root/src/arch/riscv/bootblock.S
AgeCommit message (Expand)Author
2018-09-14arch/riscv: Only execute on hart 0 for nowPhilipp Hug
2018-07-18riscv: add CAR interface Xiang Wang
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
2017-01-16riscv: get SBI calls to workRonald G. Minnich
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
2016-06-28arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
2016-04-08Change la to li (load immediate)Ronald G. Minnich
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
2015-08-09riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-18riscv: use new-style CBFS header lookupPatrick Georgi
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich