coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-03-06	src/arch/riscv: Convert to SPDX license header	Patrick Georgi
2019-11-30	arch///early_variables.h: drop unused files	Arthur Heymans
2019-09-09	arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0	Kyösti Mälkki
2019-08-26	arch/non-x86: Use ENV_ROMSTAGE_OR_BEFORE	Kyösti Mälkki
2019-08-20	arch/non-x86: Remove use of __PRE_RAM__	Kyösti Mälkki
2019-08-03	riscv: add support for OpenSBI	Xiang Wang
2019-07-12	arch, include, soc: Use common stdint.h	Jacob Garber
2019-06-23	riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths	Xiang Wang
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Separate MMIO and PNP ops	Kyösti Mälkki
2019-02-13	riscv: Add initial support for 32bit boards	Philipp Hug
2019-02-02	riscv: Simplify payload handling	Xiang Wang
2018-12-19	arch/riscv: Define and use SBI_ENOSYS	Jonathan Neuschäfer
2018-11-05	riscv: add support for supervisor binary interface (SBI)	Xiang Wang
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-11	riscv: add physical memory protection (PMP) support	Xiang Wang
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-09-21	arch/riscv/include/arch: Don't use device_t	Elyes HAOUAS
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	arch/riscv: add missing endian.h header to io.h	Philipp Hug
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-10	riscv: update misaligned memory access exception handling	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-05	riscv: add entry assembly file for RAMSTAGE	Xiang Wang
2018-09-05	riscv: add support to check machine length at runtime	Xiang Wang
2018-09-04	riscv: add spin lock support	Xiang Wang
2018-09-04	riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page	Xiang Wang
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-08-30	riscv: update the definition of intptr_t/uintptr_t	Xiang Wang
2018-08-07	arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)	Julius Werner
2018-07-31	riscv: fix issues (timestrap & PRIu64)	Xiang Wang
2018-07-12	riscv: add include/arch/smp/ directory	Xiang Wang
2018-07-11	riscv: add support to check ISA extension	Xiang Wang
2018-07-06	riscv: use __riscv_atomic to check support A extension	Xiang Wang
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
2018-04-26	arch/riscv: Store mprv bit in size_t	Jonathan Neuschäfer
2018-04-11	arch/riscv: Remove I/O space access functions (outb, etc.)	Jonathan Neuschäfer
2018-02-20	arch/riscv: Update encoding.h and adjust related code	Jonathan Neuschäfer
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2018-02-20	arch/riscv: Don't set up virtual memory	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-11-07	arch/riscv: mprv_read_*: Mark result as earlyclobber	Jonathan Neuschäfer
2017-11-07	arch/riscv: Fix return type of mprv_read_u64	Jonathan Neuschäfer
2017-09-27	arch/riscv: Document mprv_{read,write}_* functions	Jonathan Neuschäfer
2017-07-25	src/arch: Fix checkpatch warning: no spaces at the start of a line	Martin Roth
2017-07-07	arch/*: Update Kconfig symbol usage	Martin Roth
2017-05-30	arch: Unify basic cache clearing API	Julius Werner
2017-02-20	riscv: Suppress invalid coverity errors	Martin Roth