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path: root/src/arch/riscv/include
AgeCommit message (Expand)Author
2019-09-09arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki
2019-08-26arch/non-x86: Use ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
2019-08-03riscv: add support for OpenSBIXiang Wang
2019-07-12arch, include, soc: Use common stdint.hJacob Garber
2019-06-23riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04arch/io.h: Separate MMIO and PNP opsKyösti Mälkki
2019-02-13riscv: Add initial support for 32bit boardsPhilipp Hug
2019-02-02riscv: Simplify payload handlingXiang Wang
2018-12-19arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
2018-10-08Move compiler.h to commonlibNico Huber
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14arch/riscv: add missing endian.h header to io.hPhilipp Hug
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
2018-09-04riscv: add spin lock supportXiang Wang
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
2018-07-31riscv: fix issues (timestrap & PRIu64)Xiang Wang
2018-07-12riscv: add include/arch/smp/ directoryXiang Wang
2018-07-11riscv: add support to check ISA extensionXiang Wang
2018-07-06riscv: use __riscv_atomic to check support A extensionXiang Wang
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
2018-04-11arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
2018-02-20arch/riscv: Don't set up virtual memoryJonathan Neuschäfer
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
2017-11-07arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer
2017-11-07arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer
2017-09-27arch/riscv: Document mprv_{read,write}_* functionsJonathan Neuschäfer
2017-07-25src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
2017-07-07arch/*: Update Kconfig symbol usageMartin Roth
2017-05-30arch: Unify basic cache clearing APIJulius Werner
2017-02-20riscv: Suppress invalid coverity errorsMartin Roth
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
2017-01-16riscv: get SBI calls to workRonald G. Minnich