| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-06-28 | arch/riscv/mcall: Drop debug code | Patrick Rudolph |
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang |
| 2018-07-12 | riscv: add include/arch/smp/ directory | Xiang Wang |
| 2017-12-02 | arch/riscv: Remove the current SBI implementation | Jonathan Neuschäfer |
| 2017-09-27 | arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers | Jonathan Neuschäfer |
| 2017-01-16 | riscv: Move mcall numbers to mcall.h, adjust their names | Jonathan Neuschäfer |
| 2017-01-16 | riscv: get SBI calls to work | Ronald G. Minnich |
| 2016-12-06 | arch/riscv/mcall.c: Return the correct memory base and size | Jonathan Neuschäfer |
| 2016-11-07 | riscv: Unify SBI call implementations under arch/riscv/ | Jonathan Neuschäfer |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |