| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-30 | src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode | Philipp Hug |
| 2018-09-26 | arch/riscv: Advance the PC after handling misaligned load/store | Jonathan Neuschäfer |
| 2018-09-10 | riscv: update misaligned memory access exception handling | Xiang Wang |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |