| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-06-23 | riscv: use mret to invoke M-mode payload and disable interrupts | Xiang Wang |
| 2019-02-09 | riscv: Use correct argument in a1 when invoking payload | Philipp Hug |
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |