Age | Commit message (Expand) | Author |
2020-03-06 | src/arch/riscv: Convert to SPDX license header | Patrick Georgi |
2020-01-28 | commonlib: Add commonlib/bsd | Julius Werner |
2019-12-19 | src/arch: Remove unused <stdlib.h> | Elyes HAOUAS |
2019-11-30 | arch/*/*/early_variables.h: drop unused files | Arthur Heymans |
2019-11-25 | Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol | Arthur Heymans |
2019-11-10 | lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARG | Arthur Heymans |
2019-11-10 | arch/riscv: Pass cbmem_top to ramstage via calling argument | Arthur Heymans |
2019-11-06 | arch/riscv: Use FDT from calling argument when using FIT | Arthur Heymans |
2019-11-06 | arch/riscv: Rename `stages.c` to `romstage.c` | Nico Huber |
2019-11-05 | arch/riscv: Don't link `stages.c` into ramstage | Nico Huber |
2019-10-20 | src: Remove unused 'include <string.h>' | Elyes HAOUAS |
2019-09-09 | arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0 | Kyösti Mälkki |
2019-08-26 | arch/non-x86: Use ENV_ROMSTAGE_OR_BEFORE | Kyösti Mälkki |
2019-08-20 | arch/non-x86: Remove use of __PRE_RAM__ | Kyösti Mälkki |
2019-08-08 | arch/riscv: Enable FIT support | Jonathan Neuschäfer |
2019-08-03 | riscv: add support for OpenSBI | Xiang Wang |
2019-07-28 | riscv: Remove unused headers | Patrick Rudolph |
2019-07-12 | arch, include, soc: Use common stdint.h | Jacob Garber |
2019-07-02 | arch/riscv: Make RISCV specific options depend on ARCH_RISCV | Arthur Heymans |
2019-06-28 | arch/riscv/mcall: Drop debug code | Patrick Rudolph |
2019-06-23 | riscv: workaround selfboot putting the coreboot table into prog_entry_arg | Xiang Wang |
2019-06-23 | riscv: use mret to invoke M-mode payload and disable interrupts | Xiang Wang |
2019-06-23 | riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths | Xiang Wang |
2019-06-04 | arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M | Subrata Banik |
2019-04-23 | src: Use include <console/console.h> when appropriate | Elyes HAOUAS |
2019-04-23 | src: Add missing include 'console.h' | Elyes HAOUAS |
2019-03-20 | src: Use 'include <string.h>' when appropriate | Elyes HAOUAS |
2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
2019-03-04 | arch/io.h: Separate MMIO and PNP ops | Kyösti Mälkki |
2019-03-04 | device/mmio.h: Add include file for MMIO ops | Kyösti Mälkki |
2019-02-13 | riscv: Add initial support for 32bit boards | Philipp Hug |
2019-02-09 | riscv: Use correct argument in a1 when invoking payload | Philipp Hug |
2019-02-02 | riscv: Show hart id in trap handler | Philipp Hug |
2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
2019-01-24 | riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV | Ronald G. Minnich |
2019-01-17 | riscv: create Kconfig architecture features for new parts | Ronald G. Minnich |
2019-01-16 | buildsystem: Promote rules.h to default include | Kyösti Mälkki |
2018-12-19 | arch/riscv: Don't set FPU state to "dirty" | Jonathan Neuschäfer |
2018-12-19 | arch/riscv: Define and use SBI_ENOSYS | Jonathan Neuschäfer |
2018-12-18 | arch/riscv: Don't hardcode CSR numbers anymore | Jonathan Neuschäfer |
2018-12-07 | riscv: fix non-SMP support | Philipp Hug |
2018-11-19 | src: Add required space after "switch" | Elyes HAOUAS |
2018-11-05 | riscv: add support for supervisor binary interface (SBI) | Xiang Wang |
2018-11-05 | riscv: add support to block smp in each stage | Xiang Wang |
2018-11-05 | riscv: add support smp_pause / smp_resume | Xiang Wang |
2018-10-30 | src: Add missing include <stdint.h> | Elyes HAOUAS |
2018-10-30 | riscv: simplify timer interrupt handling | Philipp Hug |
2018-10-30 | src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode | Philipp Hug |
2018-10-11 | selfboot: remove bounce buffers | Ronald G. Minnich |
2018-10-11 | riscv: add physical memory protection (PMP) support | Xiang Wang |