summaryrefslogtreecommitdiff
path: root/src/arch/riscv
AgeCommit message (Expand)Author
2016-09-12src/arch: Improve code formattingElyes HAOUAS
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer
2016-08-23arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
2016-06-28arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
2016-06-12arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer
2016-06-12arch/riscv: Add misc.c to bootblock/romstage to get udelay()Jonathan Neuschäfer
2016-06-12arch/riscv: copy read/write8/16/32 from x86Jonathan Neuschäfer
2016-06-12arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constantJonathan Neuschäfer
2016-05-03build system: remove CBFSTOOL_PRE1_OPTSPatrick Georgi
2016-05-02lib/coreboot_table: use the architecture dependent table sizeAaron Durbin
2016-05-02arch: introduce architecture dependent common variablesAaron Durbin
2016-04-21lib: add common write_tables() implementationAaron Durbin
2016-04-21lib/coreboot_table: add architecture hooks for adding tablesAaron Durbin
2016-04-21lib/bootmem: allow architecture specific bootmem rangesAaron Durbin
2016-04-21arch: only print cbmem entries in one placeAaron Durbin
2016-04-21arch: use Kconfig variable for coreboot table sizeAaron Durbin
2016-04-21arch/riscv/tables: remove confusion over write_tables()Aaron Durbin
2016-04-08Change la to li (load immediate)Ronald G. Minnich
2016-03-09Makefile: Add build-time overlap check for programs loaded after corebootJulius Werner
2016-02-22die() when attempting to use bounce buffer on non-i386.Vladimir Serbinenko
2016-02-19lib/coreboot_table: add function to allow arch code to add recordsAaron Durbin
2016-02-19RISC-V: Add more debug info to debug printksAndrew Waterman
2016-02-19RISC-V: Make inline asm usage saferAndrew Waterman
2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
2016-02-11arch/{arm64,riscv}: remove jmp_to_elf_entry() declarationAaron Durbin
2016-02-11arch: remove stage_exit()Aaron Durbin
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 13:29:51 +0000