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2018-11-19src: Add required space after "switch"Elyes HAOUAS
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-11-05riscv: add support to block smp in each stageXiang Wang
Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state. The main work of each stage is executed in a single-threaded state, and the multi-threaded state is restored by call smp_resume while booting the next stage. Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/29024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage. Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/29023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30riscv: simplify timer interrupt handlingPhilipp Hug
Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-30src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug
Pointer to opcode increases by unit uint16_t not byte. Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
These codes are written by me based on the privileged instruction set. I tested it by qemu/riscv-probe. Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28569 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer
coreboot does not set up virtual memory anymore. Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so don't use them when running the clang static analyzer. On the other hand, __riscv and __riscv_xlen need to be defined in order to select some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen selects the floating-point paths in src/arch/riscv/misaligned.c. -mabi is moved with -march for consistency. A complete list of preprocessor definitions on RISC-V can be found at https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions With this commit, scan-build produces a useful result on RISC-V. Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-26arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer
After emulating an instruction in the misaligned load/store handler, we need to increment the program counter by the size of instruction. Otherwise the same instruction is executed (and emulated) again and again. While were at it: Also return early in the unlikely case that the faulting instruction is not 16 or 32 bits long, and be more explicit about the return values of fetch_*bit_instruction. Tested by Philipp Hug, using the linuxcheck payload. Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28691 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16riscv: don't write to mstatus.XSXiang Wang
XS is a read-only field of mstatus. Unable to be write. So remove this code. Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28357 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer
On the FU540 the bootblock runs on a core without lesser privilege modes, so the medeleg/mideleg CSRs are not implemented on that core, leading to a CPU exception when these CSRs are accessed. Configure medeleg/mideleg only if the misa register indicates that S-mode is implemented on the executing RISC-V core. Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25791 Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Johanna Schander <coreboot@mimoja.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14arch/riscv: Only execute on hart 0 for nowPhilipp Hug
Only execute coreboot on hart 0 until synchronisation between hart's is ready. Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14arch/riscv: add missing endian.h header to io.hPhilipp Hug
Make it uniform as other architectures also include it in io.h Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28601 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10riscv: update mtime initializationXiang Wang
Add a interface, which is implemented by SoC. Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
Highest two bits of misa can be used to check machine length. Add code to support this. Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04riscv: add spin lock supportXiang Wang
Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
Must to set MXR, when needs to read the page which is execution-only. So make this change. Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long's bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27768 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-01riscv: remove redundancy in MakefileXiang Wang
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not needs to be bootblock. src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some compile/board/time information, which is repeated with src/lib/version.c Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27557 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31riscv: fix issues (timestrap & PRIu64)Xiang Wang
When I tried to compile the RISC-V code (202e7d4f3c), I found some errors: `PRIu64` is undefined src/arch/riscv/timestamp.c does not exist Currently RISC-V does not have the implementation and use of timestamp, so I temporarily delete the code related to timestamp in the Makefile. And define PRIu64. Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-30riscv: delete src/arch/riscv/prologue.incXiang Wang
This code was copied from x86. It is not needed for RISC-V. Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27544 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18arch/riscv: Fix makefile to only set flags for riscvMartin Roth
This was updating flags for ALL architectures, not just riscv. That was bad, and gave us errors, although they weren't fatal for some reason: i386-elf-gcc: error: missing argument to '-mcmodel=' i386-elf-gcc: error: missing argument to '-march=' i386-elf-gcc: error: missing argument to '-mabi=' This issue started from commit 5fed693a (riscv: add support for modifying compiler options) Add comments to the other 'endif' statements since they're now surrounded by a global ifeq Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/27535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18riscv: add CAR interface Xiang Wang
Add an interface to support cache as ram. Initialize stack pointer for each hart. Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-12riscv: add include/arch/smp/ directoryXiang Wang
Replicate directory layout from x86 for SMP. Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27355 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11riscv: add support to check ISA extensionXiang Wang
Add support to check ISA extension for RISC-V. Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-06riscv: use __riscv_atomic to check support A extensionXiang Wang
GCC pre-defined some macros for detecting ISA extensions. We should use these macros to detect ISA features. Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
CSRs are XLEN bits wide (i.e. the same width as general purpose registers), so size_t seems a little more correct than int. This change doesn't affect functionality because MSTATUS_MPRV already fits in 31 bits. Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-11arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer
RISC-V does not have the kind of I/O space that x86 has. Other architectures tend to leave out these definitions as well. Change-Id: I7328dae1f1fa4ef8772750244a0b11a3fa5aa88f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-02-20arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer
These exceptions were new in the Privileged Architecture spec 1.10. We need to delegate them to S-mode. Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
Update encoding.h to the version shipped with spike commit 0185d36 ("Merge pull request #165 from riscv/small_progbuf"), and copy the license header from the LICENSE file. Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Don't set up virtual memoryJonathan Neuschäfer
Due to changes in the RISC-V Privileged Architecture specification, Linux can now be started in physical memory and it will setup its own page tables. Thus we can delete most of virtual_memory.c. Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Make RVC support configurableJonathan Neuschäfer
In order to support RISC-V processors with and without the RVC extension, configure the architecture variant (-march=...) explicitly. NOTE: Spike does support RVC, but currently doesn't select ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't support RVC. Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Align trap_entry to 4 bytes, as required by specJonathan Neuschäfer
The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Remove supervisor_trap_entryJonathan Neuschäfer
coreboot only maintains a single trap entry, because it only runs in machine mode. Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
The code dealing with the old config string isn't needed anymore, because the config string has been deprecated in favor of OpenFirmware-derived devicetrees. Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
This Supervisor Binary Interface, which is based on a page of code that's provided to operating systems by the M-mode software, has been superseded by a different (currently not really documented) SBI, which is based on directly executing ECALLs instructions. Thus some of our code becomes obsolete. Just rip it out until we implement the new SBI. Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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