coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-01-16	buildsystem: Promote rules.h to default include	Kyösti Mälkki
2018-12-19	arch/riscv: Don't set FPU state to "dirty"	Jonathan Neuschäfer
2018-12-19	arch/riscv: Define and use SBI_ENOSYS	Jonathan Neuschäfer
2018-12-18	arch/riscv: Don't hardcode CSR numbers anymore	Jonathan Neuschäfer
2018-12-07	riscv: fix non-SMP support	Philipp Hug
2018-11-19	src: Add required space after "switch"	Elyes HAOUAS
2018-11-05	riscv: add support for supervisor binary interface (SBI)	Xiang Wang
2018-11-05	riscv: add support to block smp in each stage	Xiang Wang
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-30	riscv: simplify timer interrupt handling	Philipp Hug
2018-10-30	src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode	Philipp Hug
2018-10-11	selfboot: remove bounce buffers	Ronald G. Minnich
2018-10-11	riscv: add physical memory protection (PMP) support	Xiang Wang
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-10-06	arch/riscv: Update comment about mstatus initialization	Jonathan Neuschäfer
2018-10-04	arch/riscv: Adjust compiler flags for scan-build	Jonathan Neuschäfer
2018-09-26	arch/riscv: Advance the PC after handling misaligned load/store	Jonathan Neuschäfer
2018-09-21	arch/riscv/include/arch: Don't use device_t	Elyes HAOUAS
2018-09-16	riscv: don't write to mstatus.XS	Xiang Wang
2018-09-15	arch/riscv: Configure delegation only if S-mode is supported	Jonathan Neuschäfer
2018-09-14	arch/riscv: Only execute on hart 0 for now	Philipp Hug
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	arch/riscv: add missing endian.h header to io.h	Philipp Hug
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-10	riscv: update misaligned memory access exception handling	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-05	riscv: add entry assembly file for RAMSTAGE	Xiang Wang
2018-09-05	riscv: add support to check machine length at runtime	Xiang Wang
2018-09-04	riscv: add spin lock support	Xiang Wang
2018-09-04	riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page	Xiang Wang
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-08-30	riscv: update the definition of intptr_t/uintptr_t	Xiang Wang
2018-08-07	arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)	Julius Werner
2018-08-01	riscv: remove redundancy in Makefile	Xiang Wang
2018-07-31	riscv: fix issues (timestrap & PRIu64)	Xiang Wang
2018-07-30	riscv: delete src/arch/riscv/prologue.inc	Xiang Wang
2018-07-18	arch/riscv: Fix makefile to only set flags for riscv	Martin Roth
2018-07-18	riscv: add CAR interface	Xiang Wang
2018-07-17	riscv: add support for modifying compiler options	Xiang Wang
2018-07-12	riscv: add include/arch/smp/ directory	Xiang Wang
2018-07-11	riscv: add support to check ISA extension	Xiang Wang
2018-07-06	riscv: use __riscv_atomic to check support A extension	Xiang Wang
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
2018-04-26	arch/riscv: Store mprv bit in size_t	Jonathan Neuschäfer
2018-04-11	arch/riscv: Remove I/O space access functions (outb, etc.)	Jonathan Neuschäfer
2018-02-20	arch/riscv: Delegate the page fault exceptions	Jonathan Neuschäfer
2018-02-20	arch/riscv: Update encoding.h and adjust related code	Jonathan Neuschäfer
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2018-02-20	arch/riscv: Don't set up virtual memory	Jonathan Neuschäfer