coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-12-02	arch/riscv: Remove supervisor_trap_entry	Jonathan Neuschäfer
2017-12-02	riscv: Remove config string support	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer
2017-12-02	arch/riscv: Return from trap_handler instead of jumping out	Jonathan Neuschäfer
2017-12-02	arch/riscv: Unify trap return	Jonathan Neuschäfer
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-11-07	arch/riscv: Use a separate trap stack	Jonathan Neuschäfer
2017-11-07	arch/riscv: gettimer: Don't use the config string	Jonathan Neuschäfer
2017-11-07	arch/riscv: Drop mret workaround	Jonathan Neuschäfer
2017-11-07	arch/riscv: mprv_read_*: Mark result as earlyclobber	Jonathan Neuschäfer
2017-11-07	arch/riscv: Fix return type of mprv_read_u64	Jonathan Neuschäfer
2017-09-27	arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers	Jonathan Neuschäfer
2017-09-27	arch/riscv: Document mprv_{read,write}_* functions	Jonathan Neuschäfer
2017-09-27	arch/riscv: trap handler: Print load/store access width in bits	Jonathan Neuschäfer
2017-09-26	riscv: Update register address	wxjstz
2017-07-25	src/arch: Fix checkpatch warning: no spaces at the start of a line	Martin Roth
2017-07-07	arch/*: Update Kconfig symbol usage	Martin Roth
2017-06-07	src: change coreboot to lowercase	Martin Roth
2017-05-30	arch: Unify basic cache clearing API	Julius Werner
2017-02-20	riscv: Suppress invalid coverity errors	Martin Roth
2017-01-16	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-12-20	riscv: enable counters via m[us]counteren	Ronald G. Minnich
2016-12-18	riscv: Add support for timer interrupts	Ronald G. Minnich
2016-12-06	riscv: Stub out sbi_(un)mask_interrupt	Jonathan Neuschäfer
2016-12-06	arch/riscv/mcall.c: Return the correct memory base and size	Jonathan Neuschäfer
2016-11-20	riscv: map first 4GiB of physical address space	Ronald G. Minnich
2016-11-14	riscv: add a variable to control trap management	Ronald G. Minnich
2016-11-13	riscv: change payload() to pass the config string pointer as arg0	Ronald G. Minnich
2016-11-12	riscv: start to use the configstring functions	Ronald G. Minnich
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-18	arch/riscv: In trap handler, don't print SP twice	Jonathan Neuschäfer
2016-10-15	arch/riscv: Visually align trap frame information	Jonathan Neuschäfer
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
2016-10-15	arch/riscv: Remove unused bootblock_simple.c	Jonathan Neuschäfer
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-15	riscv and power8: Convert printk/while(1) to die	Jonathan Neuschäfer
2016-10-07	RISCV: update the encoding.h file.	Ronald G. Minnich
2016-09-12	src/arch: Improve code formatting	Elyes HAOUAS
2016-08-29	arch/riscv: Add missing "break;"	Jonathan Neuschäfer
2016-08-23	arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode	Jonathan Neuschäfer
2016-08-23	arch/riscv: Map the kernel space into RAM (2GiB+)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Enable U-mode/S-mode counters (stime, etc.)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Fix unaligned memory access emulation	Jonathan Neuschäfer
2016-08-23	arch/riscv: Delegate exceptions to supervisor mode if appropriate	Jonathan Neuschäfer
2016-08-23	arch/riscv: Print the page table structure after construction	Jonathan Neuschäfer
2016-08-15	arch/riscv: Improve and refactor trap handling diagnostics	Jonathan Neuschäfer