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path: root/src/arch/riscv
AgeCommit message (Expand)Author
2019-07-02arch/riscv: Make RISCV specific options depend on ARCH_RISCVArthur Heymans
2019-06-28arch/riscv/mcall: Drop debug codePatrick Rudolph
2019-06-23riscv: workaround selfboot putting the coreboot table into prog_entry_argXiang Wang
2019-06-23riscv: use mret to invoke M-mode payload and disable interruptsXiang Wang
2019-06-23riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang
2019-06-04arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_MSubrata Banik
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04arch/io.h: Separate MMIO and PNP opsKyösti Mälkki
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-02-13riscv: Add initial support for 32bit boardsPhilipp Hug
2019-02-09riscv: Use correct argument in a1 when invoking payloadPhilipp Hug
2019-02-02riscv: Show hart id in trap handlerPhilipp Hug
2019-02-02riscv: Simplify payload handlingXiang Wang
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
2019-01-17riscv: create Kconfig architecture features for new partsRonald G. Minnich
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2018-12-19arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer
2018-12-19arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer
2018-12-18arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer
2018-12-07riscv: fix non-SMP supportPhilipp Hug
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
2018-11-05riscv: add support to block smp in each stageXiang Wang
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30riscv: simplify timer interrupt handlingPhilipp Hug
2018-10-30src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-06arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
2018-09-26arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
2018-09-16riscv: don't write to mstatus.XSXiang Wang
2018-09-15arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer
2018-09-14arch/riscv: Only execute on hart 0 for nowPhilipp Hug
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14arch/riscv: add missing endian.h header to io.hPhilipp Hug
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
2018-09-04riscv: add spin lock supportXiang Wang
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang