coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-01-16	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-12-20	riscv: enable counters via m[us]counteren	Ronald G. Minnich
2016-12-18	riscv: Add support for timer interrupts	Ronald G. Minnich
2016-12-06	riscv: Stub out sbi_(un)mask_interrupt	Jonathan Neuschäfer
2016-12-06	arch/riscv/mcall.c: Return the correct memory base and size	Jonathan Neuschäfer
2016-11-20	riscv: map first 4GiB of physical address space	Ronald G. Minnich
2016-11-14	riscv: add a variable to control trap management	Ronald G. Minnich
2016-11-13	riscv: change payload() to pass the config string pointer as arg0	Ronald G. Minnich
2016-11-12	riscv: start to use the configstring functions	Ronald G. Minnich
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-18	arch/riscv: In trap handler, don't print SP twice	Jonathan Neuschäfer
2016-10-15	arch/riscv: Visually align trap frame information	Jonathan Neuschäfer
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
2016-10-15	arch/riscv: Remove unused bootblock_simple.c	Jonathan Neuschäfer
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-15	riscv and power8: Convert printk/while(1) to die	Jonathan Neuschäfer
2016-10-07	RISCV: update the encoding.h file.	Ronald G. Minnich
2016-09-12	src/arch: Improve code formatting	Elyes HAOUAS
2016-08-29	arch/riscv: Add missing "break;"	Jonathan Neuschäfer
2016-08-23	arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode	Jonathan Neuschäfer
2016-08-23	arch/riscv: Map the kernel space into RAM (2GiB+)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Enable U-mode/S-mode counters (stime, etc.)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Fix unaligned memory access emulation	Jonathan Neuschäfer
2016-08-23	arch/riscv: Delegate exceptions to supervisor mode if appropriate	Jonathan Neuschäfer
2016-08-23	arch/riscv: Print the page table structure after construction	Jonathan Neuschäfer
2016-08-15	arch/riscv: Improve and refactor trap handling diagnostics	Jonathan Neuschäfer
2016-08-15	arch/riscv: Set the stack pointer upon trap entry	Jonathan Neuschäfer
2016-08-11	arch/riscv: Fix the page table setup code	Jonathan Neuschäfer
2016-08-11	arch/riscv: Update encoding.h and dependent files	Jonathan Neuschäfer
2016-08-04	src/arch/riscv/id.S: Don't hardcode the strings	Jonathan Neuschäfer
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-28	arch/riscv: Refactor bootblock.S	Jonathan Neuschäfer
2016-07-28	arch/riscv: Only initialize virtual memory if it's available	Jonathan Neuschäfer
2016-07-28	arch/riscv: Remove spinlock code from atomic.h	Jonathan Neuschäfer
2016-07-19	arch/riscv: Enable unaligned load handling	Jonathan Neuschäfer
2016-07-18	arch/riscv: Remove enter_supervisor	Jonathan Neuschäfer
2016-07-18	arch/riscv: Change all eret instructions to .word 0x30200073 (mret)	Jonathan Neuschäfer
2016-07-14	spike-riscv: Look for the CBFS in RAM	Jonathan Neuschäfer
2016-07-14	arch/riscv: Unconditionally start payloads in machine mode	Jonathan Neuschäfer
2016-06-28	riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler	Jonathan Neuschäfer
2016-06-28	arch/riscv: Show fault PC and load address on load access faults	Jonathan Neuschäfer
2016-06-28	arch/riscv: Move _start to the beginning of the bootblock	Jonathan Neuschäfer
2016-06-24	region: Add writeat and eraseat support	Antonello Dettori
2016-06-21	riscv-spike: Move coreboot to 0x80000000 (2GiB)	Jonathan Neuschäfer
2016-06-12	arch/riscv: Compile with -mcmodel=medany	Jonathan Neuschäfer
2016-06-12	arch/riscv: Add misc.c to bootblock/romstage to get udelay()	Jonathan Neuschäfer