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2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-10arch/x86: Remove EARLY_EBDA_INIT supportArthur Heymans
This is unused now. Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-10lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARGArthur Heymans
All targets now have the _cbmem_top_ptr symbol populated via calling arguments or in the nvidia/tegra210 case worked around by populating it with cbmem_top_chipset explicitly at the start of ramstage, so the Kconfig guarding this behavior can be removed. Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04arch/x86/Kconfig: drop unused BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPElyes HAOUAS
Change-Id: I199a4b7771192abf7e7489e84db43b04776dd7b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36509 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03arch/x86: Use the stage argument to implement cbmem_topArthur Heymans
Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and a pointer to the top of lower memory if often passed via lower memory (e.g. EBDA) or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-10AUTHORS: Move src/arch/x86 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-26x86: Introduce RESET_VECTOR_IN_RAM optionMartin Roth
Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-07-07arch/x86: Clean up PIRQ_ROUTEKyösti Mälkki
This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15arch/x86/Kconfig: hide the "Bootblock behaviour" option on non-romccArthur Heymans
Selecting which cbfs prefix to load is only implemented with the romcc bootblock. Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-15arch/x86/Kconfig: Hide the prefix option on all but BOOTBLOCK_NORMALArthur Heymans
Change-Id: Icf5e8fa18bea1cdfb85b8a4999d8fccea94d16b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-26x86/acpi: Add Kconfig to toggle 8259 reportingNico Huber
Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-08arch/x86/Kconfig: Fix spelling of *successful*Paul Menzel
Change-Id: If0da91cf94aa12fe7b8670f6b181e443e3446aa1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30745 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22cbmem: Always use EARLY_CBMEM_INITKyösti Mälkki
Wipe out all remains of EARLY/LATE_CBMEM_INIT. Change-Id: Ice75ec0434bef60fa9493037f48833e38044d6e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-08toolchain: Add POSTCAR as a stage we have a toolchain forPatrick Georgi
Fixes building vb2lib for postcar. Since postcar is an x86ism, add the Kconfig options only for x86. Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29395 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22arch/x86: Implement common CF9 resetNico Huber
It's very common across many x86 silicon vendors, so place it in `arch/x86/`. Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Drop leftover ROMCC supportKyösti Mälkki
Remove the last bits of building romstage with romcc. Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-28arch/x86: Define HPET_ADDRESS_OVERRIDEKyösti Mälkki
Symbol defined in via/cx700 but also used elsewhere. Change-Id: I31d6043e71dea474de00f609b9609a628ecc6eb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26arch/x86: allow idt to be available to link in all stagesAaron Durbin
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having the interrupt handling code available to all stages. In order to do this the idt setup is moved to a C module. The vecX entries are made global so that a table of references to all the interrupt vector entry points can be used to dynamically initialize the idt. The ramification for ramstage is that exceptions are initialized later (lib/hardwaremain.c). Not all stages initialize exceptions when this Kconfig variable is selected, but bootblock for the C, stages using assembly_entry.S, and of course ramstage do. Anything left out just needs a call to exception_init() at the right location. BUG=b:72728953 Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-25arch/x86: add support for cache-as-ram pagingAaron Durbin
Processors, such as glk, need to have paging enabled while in cache-as-ram mode because the front end is agressive about fetching lines into the L1I cache. If the line is dirty and in the L1D then it writes it back to "memory". However, in this case there is no backing store so the cache-as-ram data that was written back transforms to all 0xff's when read back in causing corruption. In order to mitigate the failure add x86 architecture support for enabling paging while in cache-as-ram mode. A Kconfig variable, NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve out for page tables within the cache-as-ram region. Additionally, the page directory pointer table is also carved out of cache-as-ram. Both areas are allocated from the persist-across-stages region of cache-as-ram so all stages utilizing cache-as-ram don't corrupt the page tables. The two paging-related areas are loaded by calling paging_enable_for_car() with the names of cbfs files to load the initial paging structures from. BUG=b:72728953 Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-25arch/x86: allow timestamp source to not be TSCAaron Durbin
Some x86 platforms don't have a TSC that is invariant w.r.t. rate to get accurate timestamps. As such a different timestamp is required. Therefore, allow one to specify non-TSC timestamp source and not compile in the default x86 TSC code. BUG=b:72378235,b:72170796 Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-09-22arch/x86: Enable ebda library for romstage and postcarSubrata Banik
This patch provides a kconfig option as EARLY_EBDA_INIT to ensures user can make use of EBDA library even during early boot stages like romstage, postcar. Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06arch/x86/Kconfig: Add deprecation warnings for LATE_CBMEM_INITJonathan Neuschäfer
The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ There are two warnings: * In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that aims to explain the problem. * In src/mainboard/Kconfig (just below the mainboard selection), there's a warning which points the user at LATE_CBMEM_INIT, if such a board is selected. Also update the function that needs to be implemented, as pointed out by Keith Hui and Kyösti Mälkki. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-29arch/x86: Add Kconfig option for ACPI \_PR CPU name stringMarc Jones
Add a Kconfig option to change the \PR.CPxx name string. This provides some flexibility when working with table not generated by coreboot. Change-Id: Ibc0c56783c6da80501e2177de96a414b592cb74f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-18arch/x86: select RELOCATABLE_MODULES when POSTCAR is selectedAaron Durbin
The postcar relies on the relocatable modules support. Specifically select that dependency. Change-Id: If19c39c3f153cd5a526fdad6fe09b8c309ef024f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20635 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-18CBMEM: Add config CBMEM_TOP_BACKUPKyösti Mälkki
AGESA and binaryPI boards have no easy way to determine correct cbmem_top() location early enough when GFXUMA is enabled, so they will use these functions with EARLY_CBMEM_INIT as well. At the end of AmdInitPost() the decisions of UMA base and size have not been written to hardware yet. The decisions are stored inside AGESA heap object we cannot locate from coreboot proper until after AmdInitEnv(). Modify code such that weak backup functions are only defined for LATE_CBMEM_INIT; they are somewhat troublesome to handle. Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-04-08arch/x86: remove CAR global migration when postcar stage is usedAaron Durbin
When a platform is using postcar stage it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-02-14src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggestedMartin Roth
The four options are only used in X86: - BOOTBLOCK_SIMPLE - BOOTBLOCK_NORMAL - BOOTBLOCK_SOURCE - SKIP_MAX_REBOOT_CNT_CLEAR Move them all into src/arch/x86/Kconfig - this puts them in the chipset menu instead of general setup. Verified that this makes no significant changes to any config file. Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17909 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-12-16x86: Configure premem cbmem console sizeNaresh G Solanki
Sometime preram cbmem logs are truncated due to lack of space (default preram cbmem console size is 0xc00). Provide Kconfig option to configure preram cbmem console size so that mainboard can configure it to required value. Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28Build system: Update HAVE_CMOS_DEFAULTMartin Roth
- Don't build the cmos.default file into cbfs if USE_OPTION_TABLE isn't specified. - Don't allow HAVE_CMOS_DEFAULT if HAVE_OPTION_TABLE isn't set. Change-Id: I92401e892f09fc95d4b3fd7418cdbd10ed033fa8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
This Kconfig is deprecated, new platforms need to locate ramstage stack in CBMEM instead. Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15189 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-11arch/x86: Support "weak" BIST and timestamp save routinesLee Leahy
Not all x86 architectures support the mm register set. The default routine that saves BIST in mm0 and a "weak" routine that saves the TSC value in mm2:mm1. Select the Kconfig value BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to save the BIST and timestamp values. TEST=Build and run on Amenia and Galileo Gen2. Change-Id: I8119e74664ac3522c011767d424d441cd62545ce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15126 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloops in assembly_entry.SLee Leahy
Use Kconfig values to enable debug spinloops in assembly_entry.S. This makes it easy to debug the assembly code. TEST=Build and run on Galileo Gen2 Change-Id: Ic56bf2260b8e3181403623961874c9289f3ca945 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloopLee Leahy
Conditionally add a debug spinloop to enable easy connection of JTAG debuggers. TEST=Build and run on Galileo Gen2 with a JTAG debugger. Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15127 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-15x86: Drop CONFIG_COMPILE_IN_DSDTStefan Reinauer
This option is no longer needed, as FMAP support has been fully integrated in coreboot Change-Id: I6121b31bf946532717ba15e12f5c63d2baa95ab2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05Kconfig: hide useless options on ARM.Vladimir Serbinenko
Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03arch/x86: Allow soc/chipset to set linking addressAndrey Petrov
Until recently x86 romstage used to be linked at some default address. The address itself is not meaningful because the code was normally relocated at address calculated during insertion in CBFS. Since some newer SoC run romstage at CAR it became useful to link romstage code at some address in CAR and avoid relocation during build/run time altogether. Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-17arch/x86: Add option to disable default mmap_boot implementationAlexandru Gagniuc
On certain platforms, the boot media is either not memory-mapped, or not mapped at the top of 4G. This makes the default mmap_boot implementation unsuitable. Add an option to allow such platforms to define their own mapping implementation. Change-Id: I8293126fd9cc1fd3d75072f7811e659765348e4a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-13x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurableAaron Durbin
Certain platforms may need to limit their bootblock size to within a given size because specific constraints. Allow the size to be provided by the mainboard or chipset by way of the arch Kconfig being processed after those. Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13691 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-11arch/x86: Change how BOOTBLOCK_CUSTOM is selected by defaultAndrey Petrov
Currently x86s select BOOTBLOCK_CUSTOM by default. With this change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't. Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13642 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-03xcompile: Add a way to specify -march=i586Martin Roth
Instead of instructing users to edit xcompile when they want to build a quark platform, give the build a way to set -march=586 so that the quark code will build correctly. The Quark processor does not support the instructions introduced with the Pentium 6 architecture. Change-Id: I0ed69aadc515f86f76800180e0e33bcd75feac5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13552 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-23acpi: bring back ability to link DSDT into ramstagePatrick Georgi
Bring back the ability to link in the DSDT. This is to help Chrome OS to switch over to a new upstream quickly (because some of the custom built mechanisms are a pain with tons of files). This is supposed to be temporary (famous last words), but I'd rather fix the lack of CBFS awareness in CrOS bit for good in the time I usually spend on keeping upstream and CrOS branches close. Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-16Add x64 support to src/arch/x86/KconfigStefan Reinauer
Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8692 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10x86: Support reset routines in bootblockLee Leahy
Expand the boot block include file to allow for a file containing reset routines to be added. Prevent breaking existing platforms by using a Kconfig value to specify the path to this file, and have the code include this file only if the Kconfig value is set. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51 Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9504 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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