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2021-05-18option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons
Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"Arthur Heymans
Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06arch/x86: Always include walkcbfs.SArthur Heymans
Let the linker decide if this code is needed. Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-04arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=nArthur Heymans
TESTED on qemu/i440fx with VBOOT_SEPARATE_VERSTAGE commented out. Change-Id: I1227feab9ffbbc06e614f297be44fb67f13bda42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52784 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry32.incKyösti Mälkki
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08arch/x86/Makefile.inc: Clean up generated assembly stubsArthur Heymans
At the moment neither verstage nor romstage has a generated assembly stub. This was used when CAR was set up in romstage which is not the case anymore. Change-Id: Ia4a952f269cc2b3edf1290c80b7a63619c8c6c95 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-16arch/x86: Link gdt_init.S into bootblockKyösti Mälkki
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19ACPI S3: Split arch-agnostic partsKyösti Mälkki
Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-19arch/x86/boot: Jump to payload in protected modePatrick Rudolph
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-14arch/x86/postcar: Add x86_64 supportPatrick Rudolph
* Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30arch/x86/smbios.c: Split out weak functionsAngel Pons
The `smbios.c` file is rather long. To improve navigability, place weak function definitions on a separate compilation unit. Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08arch/x86: Add memmove.c to x86 bootblockMartin Roth
This was specifically needed for vboot with psp_verstage, but adding it to always be built into bootblock if needed like memcpy & memset makes sense. TEST=Build & boot trembyle BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-06arch/x86: Remove RELOCATABLE_RAMSTAGEKyösti Mälkki
We always have it, no need to support opting-out. For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage located inside CBMEM, which is only true with ARCH_X86. Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05arch/x86/Makefile.inc: Drop unused reset.c ruleAngel Pons
No x86 mainboard has a reset.c file. Change-Id: I167629c7addf485944926d57cf0228606c0f32e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42582 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src/arch/x86: Ensure $(objgenerated) exists before it's usedPatrick Georgi
In some rare cases it seems that make tries to build $(objgenerated)/assembly.inc before the build-dirs target has finished, and so assembly.inc can't be written. Enforce that build-dirs is done before assembly.inc starts. BUG=chromium:1098215 BRANCH=none TEST=none Change-Id: Ib141ea45a43836cfdde0059523c331fe5286b06d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15Makefile.inc: Remove all-y with CONFIG_ARCH_xx guardsMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. As a generalization, remove all-y for CONFIG_ARCH_xx guarded makefiles. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10arch/x86: Remove some x86_32 vs x86_64 noiseKyösti Mälkki
Change-Id: Ib98483e5d6fcd66fdc72f6157a5bf185fef13016 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (5/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 5/5 which moves the addition of ACPI table related files from arch/x86/Makefile.inc to acpi/Makefile.inc. BUG=b:155428745 Change-Id: I8143fd37357aeb0561516450adddc6714d539ada Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (1/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 1/5 which moves .c files from arch/x86 to acpi/. The only acpi files that are still retained under arch/x86 are: a. acpi_s3.c: This doesn't really deal with ACPI tables. Also, there are some assumptions in there about SMM which will have to be resolved if this file needs to be moved to common code. b. acpi_bert_storage.c/bert_storage.h: This file is currently written specifically with x86 in mind. So, not moving the file for now. Motivation for this change: Not all stages on Picasso SoC are targeted for the same architecture. For example, verstage (if runs before bootblock) will be targeted for non-x86. This makes it difficult to add device tree to verstage which would be required to get to SoC configs from the tree. This is because the device tree on x86 platforms currently contains a lot of devices that require ACPI related enums and structs (like acpi_gpio, acpi_pld, acpi_dp and so on). Hence, this change removes all ACPI table support out of arch/x86. BUG=b:155428745 Change-Id: Icc6b793c52c86483a8c52e0555619e36869a869e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-20arch/x86/acpi: Add code to generate ACPI for PS2 keyboardsRajat Jain
Add new file to generate ACPI _DSD code for PS2 keyboards. The following 2 device properties are generated as needed: function-row-phymap: A list of ordered scancodes for function row. linux,keymap: Symantically, this is an array of "scancode,keycode" tuple entries. Each entry teaches linux the keycode corresponding to a scancode. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I5ee05173106a125793e91c263610731543c85472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-25arch/x86: Add Kconfig option for 2nd VGA BIOS imageMartin Roth
Picasso and Dali need different video bioses even though they use the same code in most other places. The Kconfig symbol names are changed from the downstream commit to make them more consistent with current coreboot code. BUG=b:145817712 TEST=Build Dali vBIOS into the coreboot image Change-Id: Ide0d061fda0abc78a74ddf97ba81fc3cf2b02e4f Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1956534 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-03-06src/arch/x86: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-14console/post: Split parts to arch/Kyösti Mälkki
Both IO port and cmos are currently arch/x86 only features. Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27cpu/intel/microcode: Apply more strict guard for assembly filesKyösti Mälkki
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27arch/x86: Remove walkcbfs()Kyösti Mälkki
This was used in romcc bootblocks. Change-Id: Ie0cfbf124922d04a3320404d667610ad369ec00b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-27bootblock: Support normal/fallback mechanism againKyösti Mälkki
Change-Id: I7395e62f6682f4ef123da10ac125127a57711ec6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37760 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20arch/x86: Drop romcc bootblockArthur Heymans
Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src/arch/x86: Build mainboard acpi_tables source if presentKarthikeyan Ramasubramanian
Current build rules require adding blank acpi_tables in some of the mainboards (eg. octopus, hatch). Update the build rules to compile the acpi_tables.c only if it is present. This will help to avoid adding blank acpi_tables.c source file. BUG=None TEST=Build test with octopus and hatch without blank acpi_table.c file. Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-22Makefiles: Remove -D__PRE_RAM__Kyösti Mälkki
All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from <rules.h>. Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21arch/x86: Remove copy_and_run()Kyösti Mälkki
Nothing but a wrapper for run_ramstage() with an ugly name. Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-10arch/x86: Remove EARLY_EBDA_INIT supportArthur Heymans
This is unused now. Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-06arch/x86: Create preprocessed __ROMCC__ bootblock sourceKyösti Mälkki
Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-03arch/x86: Use the stage argument to implement cbmem_topArthur Heymans
Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and a pointer to the top of lower memory if often passed via lower memory (e.g. EBDA) or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-30arch/x86/Makefile.inc: Use the 'all' target to add common sourcesArthur Heymans
Change-Id: Ibbd418656c32f56be2b00481068e8499421b147c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30arch/x86: Fix __ROMCC__ automatic prerequisitiesKyösti Mälkki
While the list of prerequisities is not created with romcc, we need to simulate it since different set of header files will is used. Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/arch/x86 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06Makefile.inc: Compile smm files independent ARCH_RAMSTAGE_X86_32/64Subrata Banik
This patch makes smm related files compile independent of ramstage getting compiled. If user selects RAMPAYLOAD to boot without ramstage, there will be need for smm code to get compiled independently. Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02Makefile.inc: Remove unnecessary CONFIG dependencySubrata Banik
This patch removes unnecessary kconfig depencies as below 1. CONFIG_ARCH_RAMSTAGE_X86_32 2. CONFIG_RELOCATABLE_RAMSTAGE Include required files as is without specify kconfig option. Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-03-16device/pci_ops: Have only default PCI bus ops availableKyösti Mälkki
In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops. This change effectively inlines all PCI config accessors for ramstage as well. Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07src/device/Kconfig: Include the discrete VGA OpROM at config UIMike Banon
Create the way of adding the discrete VGA OpROM at config UI (alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_VGA_BIOS is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-20walkcbfs: Only compile on x86_32Patrick Rudolph
The current implementation was designed for x86_32, so don't attempt to compile it on x86_64 until it is fixed. Fixes compilation error on x86_64. Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08arch/x86: Link walkcbfs.S instead of including itArthur Heymans
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the romstage. This is useful for cbfs access in pre-CAR environments. Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 08:08:37 +0000