summaryrefslogtreecommitdiff
path: root/src/arch/x86/bootblock_crt0.S
AgeCommit message (Collapse)Author
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-24soc/intel/quark: Drop BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPKyösti Mälkki
This was empty stub call doing nothing, to avoid targeting non-existing MMX registers. Change-Id: I78b83e6724159ea1eb0f8a0cf9d5b7ddfc9877b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-06-11arch/x86: Support "weak" BIST and timestamp save routinesLee Leahy
Not all x86 architectures support the mm register set. The default routine that saves BIST in mm0 and a "weak" routine that saves the TSC value in mm2:mm1. Select the Kconfig value BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to save the BIST and timestamp values. TEST=Build and run on Amenia and Galileo Gen2. Change-Id: I8119e74664ac3522c011767d424d441cd62545ce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15126 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloopLee Leahy
Conditionally add a debug spinloop to enable easy connection of JTAG debuggers. TEST=Build and run on Galileo Gen2 with a JTAG debugger. Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15127 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09arch/x86: Enable SSE in bootblock_crt0.SLee Leahy
Don't write reserved bits in the Quark platform. Follow the previous boot behavior and just enable SSE. TEST=Build and run on Galileo Gen2 Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-15bootblock_crt0: Use CR* macros from cpu/x86/cr.hFurquan Shaikh
Instead of re-defining the macros, include cpu/x86/cr.h in bootblock_crt0.S to re-use already defined macros for accessing CR* flags. Change-Id: Idade02f7a6bc880c9aad3bfacd05ac57b6d04e44 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14359 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-02arch/x86: Add second paragraph to license headerMartin Roth
Change-Id: Ic1da46d2abc8d20987048e4ef1e7a776d0c685d6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13555 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-30arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCKAlexandru Gagniuc
Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>