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2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-07arch/*: Update Kconfig symbol usageMartin Roth
- Update all symbols to use IS_ENABLED() - Update non-romcc usage to use 'if' instead of '#if' where it makes sense. Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20005 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-08arch/x86/acpigen: Add additional opcodesPatrick Rudolph
Add additional ACPI opcodes, that are going to be used in the following commits. Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-30arch: Unify basic cache clearing APIJulius Werner
Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-30arch/x86: Add function to determine if we're currently running from CARJulius Werner
This patch adds a simple function that can be used to check if CAR_GLOBALs are currently being read from CAR or from DRAM. Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22arch/x86/include: Use IS_ENABLED() macroNico Huber
Change-Id: I0f9a92e595ec765d47f89f0023ff69636ee406af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-25arch/x86: Add read64 and write64 functionsMarshall Dawson
Create new functions similar to read and write of other sizes. Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19394 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-08arch/x86: remove CAR global migration when postcar stage is usedAaron Durbin
When a platform is using postcar stage it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-03arch/x86/acpigen: Allow writing buffers larger than 256 bytesRizwan Qureshi
Currently only 256 bytes can be written at a time using the acpigen_write_return_byte_buffer or acpigen_write_byte_buffer API's and there can be cases where the buffer size can exceed this, hence increase the number of bytes that can be written. Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-20arch/x86: Fix most of remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: do not use assignment in if condition ERROR: trailing statements should be on next line ERROR: Macros with complex values should be enclosed in parentheses ERROR: switch and case should be at the same indent WARNING: char * array declaration might be better as static const WARNING: else is not generally useful after a break or return WARNING: storage class should be at the beginning of the declaration WARNING: void function return statements are not generally useful WARNING: break is not useful after a goto or return WARNING: Single statement macros should not use a do {} while (0) loop WARNING: sizeof *t should be sizeof(*t) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-17arch/x86: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix prefer errors detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: plain inline is preferred over __inline__ TEST=Build and run on Galileo Gen2 Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18863 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix space issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: space prohibited after that open square bracket '[' ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ';' (ctx:VxV) ERROR: spaces required around that ':' (ctx:ExV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: spaces required around that ':' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '||' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxO) ERROR: need consistent spacing around '+' (ctx:WxV) ERROR: spaces required around that '<' (ctx:WxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: "(foo*)" should be "(foo *)" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: unnecessary whitespace before a quoted newline WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix issues with braces detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line ERROR: that open brace { should be on the previous line ERROR: else should follow close brace '}' WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16acpi_device: Add macro for GpioInt that uses both polarityDuncan Laurie
GPIO edge interrupts can report that they are ActiveBoth and will generate an interrupt event on both rising and falling edges. Add a macro so this type of GPIO interrupt can be used. BUG=b:35581264 BRANCH=none TEST=successfully use this interrupt type on Eve Change-Id: I91408386538e442bddcacc9840e0aa14370a446c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Prefix IRQ macros with ACPIDuncan Laurie
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not fail at compile time if they are used. BUG=b:35581264 BRANCH=none TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15acpi: device: Add macro for active high level triggered IRQDuncan Laurie
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get used by devicetree when necessary. BUG=b:35585307 BRANCH=none TEST=Add rt5514 SPI device with active high level IRQ on Eve board and check that it is enumerated in the kernel Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-02acpi: Update the ACPI ID for corebootDuncan Laurie
The newly assigned ACPI ID for coreboot is 'BOOT' http://www.uefi.org/acpi_id_list Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific ACPI objects instead of the placeholder range of "GOOGCBxx". Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-24src/arch/x86: Remove non-ascii charactersMartin Roth
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18376 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-22arch/x86/acpigen: Provide helper functions for enabling/disabling GPIOFurquan Shaikh
In order to allow GPIOs to be set/clear according to their polarity, provide helper functions that check for polarity and call set/clear SoC functions for generating ACPI code. BUG=None BRANCH=None TEST=Verified that the ACPI code generated remains the same as before for reef. Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-19acpi_device: Add macros for GPIO interruptsDuncan Laurie
Add individual macros for the various interrupt types so they can be used in devicetree. BUG=chrome-os-partner:58666 TEST=nothing uses this yet, will be used in an upcoming commit Change-Id: I2a569f60fcc0815835615656b09670987036b848 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18392 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19acpi_device: Move power resource function to generic codeDuncan Laurie
Move the function that adds a power resource block from i2c/generic to the acpi device code at src/arch/x86/acpi_device.c so it can be used by more drivers. BUG=chrome-os-partner:61233 TEST=verify SSDT table generation is unchanged Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-16spi: Add function callback to get configuration of SPI busFurquan Shaikh
Add a new callback to spi_ctrlr structure - get_config - to obtain configuration of SPI bus from the controller driver. Also, move common config definitions from acpi_device.h to spi-generic.h BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-04x86/acpi: Add VFCT tablePatrick Rudolph
Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-06arch/x86: fix cmos post logging in non romcc bootblockAaron Durbin
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18043 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-16acpi_device: Add special HID for DT namespaceFurquan Shaikh
BUG=chrome-os-partner:60194 BRANCH=None TEST=Compiles successfully Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-11ACPI S3: Hide acpi_slp_typeKyösti Mälkki
Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/10360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09postcar_loader: Support LATE_CBMEM_INIT boardsKyösti Mälkki
Create postcar_frame object without placing stack in CBMEM. This way same cache_as_ram.inc code can be used unmodified. Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06PCI ops: Rename pcie_xx() to pci_mmio_xx()Kyösti Mälkki
Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17530 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-24arch/x86/acpigen: Write DSM method with multiple UUID'sNaresh G Solanki
Enable generic way of writing DSM method which can write acpi table for multiple UUID's. Change-Id: Ic1fbdc0647e8fdc50ffa407887feb19a63cb48e4 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17424 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-17arch/x86/acpigen: Implement acpigen functions to return integer & stringNaresh G Solanki
Add ACPI method to return integer & string. Change-Id: I2a668ccadecb71b71531e2eb53a52015fca96738 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16arch/x86/acpigen: Fix acpigen for If (Lequal (...))Furquan Shaikh
acpigen_write_if_lequal is used to generate ACPI code to check if two operands are equal, where operand1 is an ACPI op and operand2 is an integer. Update name of function to reflect this and fix code to write integer instead of emitting byte for operand2. TEST=Verified by disassembling SSDT on reef that ACPI code generated for If with operand2 greater than 1 is correct. If ((Local1 == 0x02)) { Return (0x01) } Else { Return (Buffer (One) { 0x00 /* . */ }) } Change-Id: If643c078b06d4e2e5a084b51c458dd612d565acc Reported-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-07arch/x86/acpigen: Add OperationRegion & Field methodNaresh G Solanki
Add acpigen_write_opregion that generates ACPI AML code for OperationRegion, region name, region space, region length & region size are inputs. Add acpigen_write_field that generates ACPI AML code for Field. Operation region name & field list are inputs. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17113 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-25arch/x86/acpigen_dsm: Add support for DSM typesFurquan Shaikh
Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25arch/x86/acpigen: Add support for _DSM method generationFurquan Shaikh
Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17090 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25arch/x86/acpigen: Add more functions to ACPIGEN libraryFurquan Shaikh
1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17088 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24arch/x86/acpigen: Add support for interacting with GPIOsFurquan Shaikh
Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17080 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24arch/x86/acpigen: Add new functions to acpigen libraryFurquan Shaikh
Add functions to support generation of following AML operations: 1. PowerResource 2. Store 3. Or 4. And 5. Not 6. Debug 7. If 8. Else 9. Serialized method BUG=chrome-os-partner:55988 Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17079 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-24arch/x86/acpigen: Clean up acpigen libraryFurquan Shaikh
Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17078 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-07x86/acpi_device: Add support for GPIO output polarityFurquan Shaikh
Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-27x86: acpi: Use GOOG ID for coreboot tableDuncan Laurie
Use the GOOG ACPI ID until there is an official ID allocation for coreboot. Since I administer this range I allocated 0xCB00-0xCBFF for coreboot use. Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 11:15:58 +0000