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2019-01-10northbridge/amdfam10: Deal with PCI_ADDR() betterKyösti Mälkki
PCI_ADDR() is tightly coupled with different setup_resource_map() variants so move the declaration away from global namespace. In the implementation of setup_resource_map() use the bottom 12 bits as the register mask like the other variants do already. Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30784 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10arch/x86: Remove weak tsc_freq_mhz() implementationKyösti Mälkki
Build with TSC_CONSTANT_RATE must fail when this function is not implemented for the platform. Weak implementation causes division by zero in timer_monotonic_get() and turns udelay() into no delay. Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-08arch/x86/Kconfig: Fix spelling of *successful*Paul Menzel
Change-Id: If0da91cf94aa12fe7b8670f6b181e443e3446aa1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30745 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08arch/x86: Link walkcbfs.S instead of including itArthur Heymans
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the romstage. This is useful for cbfs access in pre-CAR environments. Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08arch/x86: Unify bootblock MMX register usageKyösti Mälkki
Have same usage of registers with romcc bootblock and C_ENVIRONMENT_BOOTBLOCK. Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-07usbdebug: Initialize the HW once in CAR stagesArthur Heymans
The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-04amdfam10 boards: Add Makefiles and fix resourcemap.cKyösti Mälkki
Also remove global ramstage-y += get_bus_conf.c, this is specific to amdfam10. Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04src: Move {pci,pnp}_devfn_t to common 'device/pci_type.h'Elyes HAOUAS
Definitions of these types are arch-agnostic. Shared device subsystem files cannot include arch/pci_ops.h for ARM and arch/io.h for x86. Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-04src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30047 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-30arch/x86: Add CAR stack location symbolsKyösti Mälkki
Add symbols for the non C_ENVIRONMENT_BOOTBLOCK builds and use them for stack guards. Change-Id: Ib622eacb161d9a110d35a7d6979d1b601503b6f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30arch/x86: Use a common timestamp.inc with romcc bootblocksKyösti Mälkki
The same file was replicated three times for certain soc/intel bootblocks, yet there are no indications or need to do chipset-specific initialisation. There is no harm in storing the TSC values in MMX registers even when they would not be used. Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30arch/x86: Prevent romcc bootblock from using MMX registersKyösti Mälkki
Platforms with SSE=y or SSE2=y will invoke romcc with -mcpu=k7. This implicitly enabled romcc to consume MMX registers, if XMM set was consumed first. Explicitly tell romcc not to clobber MMX set. Change-Id: I37f1d6ea01873036712dfbb32bb1dcd5d769e85d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28arch/x86/c_start.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I415993bf11f6a019ff8ef4c0cba3b5bb511271fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30453 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki
Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24soc/intel/quark: Drop BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPKyösti Mälkki
This was empty stub call doing nothing, to avoid targeting non-existing MMX registers. Change-Id: I78b83e6724159ea1eb0f8a0cf9d5b7ddfc9877b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-24arch/x86/wakeup.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-22cbmem: Always use EARLY_CBMEM_INITKyösti Mälkki
Wipe out all remains of EARLY/LATE_CBMEM_INIT. Change-Id: Ice75ec0434bef60fa9493037f48833e38044d6e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-22arch/x86 cbmem: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Remove all cases in code where we tested for EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set. This also removes all references to LATE_CBMEM_INIT in comments. Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26827 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-05arch/x86/include/stdint: Fix PRIu64Patrick Rudolph
We alwas define uint64_t as unsigned long long, even on x86_64. Fix PRIu64 to match the definition of the datatype, to prevent compilation errors when compiling for x86_64. Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-04acpi_pld: Make it easier to define the ACPI USB device groupsDuncan Laurie
The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29arch/acpi.h: Add some update to version 6.2aElyes HAOUAS
Some tables updated to comply with ACPI version 6.2a. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-29arch/x86/acpigen.c: Add a method to notify all CPU coresArthur Heymans
Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29arch/x86/Makefile.inc: Fix typoPatrick Rudolph
Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23arch/x86: drop special case cbfs locatorPatrick Georgi
CBFS used to have a special region for the x86 bootblock, which also contained a pointer to a CBFS master header, which describes the layout of the CBFS. Since we adopted other architectures, we got rid of the bootblock region as a separate entity and add the x86 bootblock as a CBFS file now. The master header still exists for compatibility with old cbfstool versions, but it's neatly wrapped in either the bootblock file or in a file carefully crafted at the right location (on all other architectures). All the layout information we need is now available from FMAP, a core part of a contemporary coreboot image, even on x86, so we can just use the generic master header locator in src/lib/cbfs.c and get rid of the special version. Among the advantages: the x86 header locator reduced the size of the CBFS by 64 bytes assuming that there's the bootblock region of at least that size - this breaks assumptions elsewhere (eg. when walking CBFS in cbfs_boot_locate() because the last file, the bootblock, will exceed the CBFS region as seen by coreboot (since it's CBFS - 64bytes). TEST=emulation/qemu-q35 still boots Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23src/arch/x86/acpi.c: Create log area and extend TPM2 tableMichał Żygowski
According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-23soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-14mb/emulation/qemu-i440fx|q35: Fix stack sizePatrick Rudolph
Current implementation works by luck as DCACHE area is actually RAM and stack can grow and use that RAM outside of the area. * Set DCACHE_BSP_STACK_SIZE to 0x4000. * Add an assert to make sure it is set to a sane value on all platforms. Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29611 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATIONFurquan Shaikh
Change 76ab2b7 ("arch/x86: allow global .bss objects without CAR_GLOBAL") allowed use of global .bss objects and hence moved around the macros resulting in car_active returning 0 even for those boards where CAR is actually active but do not require global migration. This resulted in boards getting stuck when doing a reset in verstage because the code flow incorrectly assumed that there was no CAR active and hence triggered a cache invalidate. This change fixes the above issue by returning 1 for car_active if ENV_CACHE_AS_RAM is set even if global migration is not required. BUG=b:109717603 TEST=Verified that board reset does not trigger cache invalidate in verstage and does not result in board hang. Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-09include/program_loading: Add POSTCAR prog typePhilipp Deppenwiese
Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-08toolchain: Add POSTCAR as a stage we have a toolchain forPatrick Georgi
Fixes building vb2lib for postcar. Since postcar is an x86ism, add the Kconfig options only for x86. Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29395 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-06x86/acpi.c: Be more verbose when finding the wakeup vectorAngel Pons
Since S3 resume sometimes breaks when trying to find the wakeup vector, it is useful to log whether it errors or not. Since it is an error, print it as such. Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01arch/x86: clarify raw CAR_GLOBAL access guardsAaron Durbin
Romstage is where DRAM comes online. Therefore, allow raw CAR_GLOBAL object access in all cache-as-ram stages that are not romstage. In practice, this should be a nop. However, the explicit check for romstage is clearer. Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-01arch/x86: allow global .bss objects without CAR_GLOBALAaron Durbin
For platforms utilizing CONFIG_NO_CAR_GLOBAL_MIGRATION there's no need to automatically migrate globals. Because of this it's possible to automatically allow for uninitialized global variables which reside in the .bss section without needing to decorate those objects with CAR_GLOBAL. Change-Id: Icae806fecd936ed2ebf0c13d30ffa07c77a95150 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-26arch/x86/acpi: Add TPM2 table supportPhilipp Deppenwiese
* Distinguish between TPM 1.2 and 2.0 ACPI table support * Add TPM2 table support for TIS interface only Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/29181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23acpi_device: Refine ACPI_IRQ_* macrosFurquan Shaikh
This change does the following: 1. Adds a helper macro ACPI_IRQ_CFG that can be used by all other ACPI_IRQ* macros to initialize acpi_irq structure. 2. Provides ACPI_IRQ_WAKE* versions to allow board to define an irq as wake capable. BUG=b:117553222 Change-Id: Ic53c6019527bbd270806897247f547178cd1ad3c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-22arch/x86: Implement common CF9 resetNico Huber
It's very common across many x86 silicon vendors, so place it in `arch/x86/`. Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-17arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer
Add punctuation and fix a typo. Change-Id: Ic61c665f7e2daefb50b478a1710ea66c8a88235a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04arch/x86: Make mb/romstage.c optionalRizwan Qureshi
Currently src/mainboard/*/romstage.c is mandatory for compiling, this makes having the file present even though there is nothing to initialize in romstage on the mainboard side. Eliminate the need to have empty romstage.c files using the wildcard function. BUG=None BRANCH=None TEST= build cannonlake_rvp after removing the romstage.c file. Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-09-16acpi: Call acpi_gen_writeSTA by status from device treeHung-Te Lin
The device tree now supports 'hidden' and the status can be found in `struct device.hidden`. A new acpi_device_status() will return the expected setting of STA from a `struct device`. BUG=b:72200466 BRANCH=eve TEST=Builds and boots properly on device eve Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28567 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706Richard Spiegel
There are 8 possible BERT context errors, with table ctx_names being a table to print their names. Thus the table is supposed to have 8 elements, and indeed it has 8 lines... but some lines are missing commas, and when compiling it becomes a 5 element table. Add the commas at the appropriate places. BUG=b:115719190 TEST=none. Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-09-14arch/x86/acpigen: Fix comment in _ROM method generatorJonathan Neuschäfer
Commit 24462e6507 ("x86/acpigen: Fix ACPI _ROM method") changed the code to generate a serialized method, but didn't adjust the comment. Change-Id: Ie7dbaff13d36f31e9d627609d0f74a4e9fa5a1e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 12:27:24 +0000