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2020-06-13arch/x86: Add symbols for CAR MTRRs in linker scriptKyösti Mälkki
This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Also, linker scripts have LOG2CEIL which comes in handy to enforce MTRR alignments. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13arch/x86: Include id.ld unconditionally in memlayout.ldFurquan Shaikh
Now that Picasso uses its own memlayout.ld, always include id.ld in arch/x86/memlayout.ld. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I04b59c2a273cad0a2e64dbc325c0b09fca254558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42266 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13arch/x86: Drop early_ram.ldFurquan Shaikh
Now that Picasso uses its own linker script, early_ram.ld from arch/x86 is unused and hence is dropped as part of this change. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ida83d40d005ddab789628a1581389fc487b10d4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10arch/x86: Remove some x86_32 vs x86_64 noiseKyösti Mälkki
Change-Id: Ib98483e5d6fcd66fdc72f6157a5bf185fef13016 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-09SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPEKyösti Mälkki
This gets rid of the magic numbers in Kconfig. Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-02arch/x86/postcar_loader: utilize var_mtrr_context APIAaron Durbin
Now that there is a generic solution in mtrr subsystem utilize the API. BUG=b:155426691,b:155322763 Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28arch/x86: Fix id section in linker scriptKyösti Mälkki
Builds where RESET_X86_VECTOR is adjusted would create unintentionally large bootblock files since id section can move far away from .reset and .text. Some builds segfault or may try to create close to 4 GB large intermediate build objects. For cases where build is successful, id section would not reside within REGION(program) or REGION(bootblock). A proper fix to always place the ID data at the end of the coreboot.rom file is left as follow-up work. For now, just place id section below .reset. Change-Id: Idf0e4defcde6d5e264d4752cc93f4ffb6749d287 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28arch/x86: Remove more romcc leftoversKyösti Mälkki
The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-26Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTIONKyösti Mälkki
After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18arch/x86/early_ram.ld: Add vboot work bufferRaul E Rangel
This is required to enable VBOOT_STARTS_IN_BOOTBLOCK and VBOOT_SEPARATE_VERSTAGE for picasso. BUG=b:147042464 TEST=Boot verstage on picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3e261a6919a78760d567be9cc684494a5aeab6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-18x86/include/arch/mmio.h: Convert to 96 characters line lengthElyes HAOUAS
Change-Id: I93d0ef6db417904c345fe7b76730bcb70ba25089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41361 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07arch/x86: unexpose postcar_frame_common_mtrrs()Aaron Durbin
The only caller is contained within the postcar_loader compilation unit. Therefore, remove postcar_frame_common_mtrrs() from the global symbol namespace. Change-Id: I90d308669d13eb2bebf1eca4d47e3f3b4f178714 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02acpi: Reorganize ACPI configsFurquan Shaikh
In order to the Kconfigs in the same directory where the corresponding code lives, this change moves ACPI_BERT to arch/x86/Kconfig and following configs to acpi/Kconfig: ACPI_CPU_STRING ACPI_HAVE_PCAT_8259 ACPI_NO_PCAT_8259 HAVE_ACPI_TABLES BUG=b:155428745 Change-Id: I289565f38e46bd106ff89685aaf8f57e53d9827a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40932 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (5/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 5/5 which moves the addition of ACPI table related files from arch/x86/Makefile.inc to acpi/Makefile.inc. BUG=b:155428745 Change-Id: I8143fd37357aeb0561516450adddc6714d539ada Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (4/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 4/5 which gets rid of the placeholder header files that were added to temporarily include acpi/ header files from arch/header files. BUG=b:155428745 Change-Id: If6e8580c3c6433f9239e06a1dc7ba661b3f597e5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02acpi: Move ACPI table support out of arch/x86 (2/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 2/5 which moves the contents of arch/x86/include/arch/acpi*.h files into include/acpi/acpi*.h and updates the arch header files to include acpi header files. These are just temporary placeholders and will be removed later in the series. BUG=b:155428745 Change-Id: I9acb787770b7f09fd2cbd99cb8d0a6499b9c64b3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02acpi: Move ACPI table support out of arch/x86 (1/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 1/5 which moves .c files from arch/x86 to acpi/. The only acpi files that are still retained under arch/x86 are: a. acpi_s3.c: This doesn't really deal with ACPI tables. Also, there are some assumptions in there about SMM which will have to be resolved if this file needs to be moved to common code. b. acpi_bert_storage.c/bert_storage.h: This file is currently written specifically with x86 in mind. So, not moving the file for now. Motivation for this change: Not all stages on Picasso SoC are targeted for the same architecture. For example, verstage (if runs before bootblock) will be targeted for non-x86. This makes it difficult to add device tree to verstage which would be required to get to SoC configs from the tree. This is because the device tree on x86 platforms currently contains a lot of devices that require ACPI related enums and structs (like acpi_gpio, acpi_pld, acpi_dp and so on). Hence, this change removes all ACPI table support out of arch/x86. BUG=b:155428745 Change-Id: Icc6b793c52c86483a8c52e0555619e36869a869e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-02arch/x86: Change power_res_dev_states[] to be static const * constFurquan Shaikh
This change makes power_res_dev_states[] to be static const * const as complained by Jenkins. BUG=b:155428745 Change-Id: Ice2fff6ab3bcd72a059bc905b7462a681f2e6aaf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-02cpu: Add a helper function cpu_get_lapic_addrFurquan Shaikh
This change adds a helper function cpu_get_lapic_addr() that returns LOCAL_APIC_ADDR for x86. It also adds a weak default implementation which returns 0 if platform does not support LAPIC. This is being done in preparation to move all ACPI table support in coreboot out of arch/x86. BUG=b:155428745 Change-Id: I4d9c50ee46804164712aaa22be1b434f800871ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-01acpi_device: Make integer array input variable constDuncan Laurie
An array of 64bit integers is passed to acpi_dp_add_integer_array() but it is not const so can't take a const array without a compiler error. The function does not modify the array so it can be made const without breaking anything and allowing a const array to be passed in the future. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01arch/x86/acpi: Add define for generic container HIDDuncan Laurie
The generic container HID is defined in ACPI specification as PNP0A05. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01arch/x86/acpi_device: Allow empty child referencesDuncan Laurie
Currently if a child table is created and added to a property list without adding any properties to that child it will generate an empty package. For example: struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); struct acpi_dp *prop = acpi_dp_new_table("PROP"); acpi_dp_add_child(dsd, "dsd-prop", prop); acpi_dp_write(dsd); Results in an empty PROP package: Name (_DSD, Package (2) { ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") Package (1) { Package (2) { "dsd-prop", "PROP" } } } Name (PROP, Package (0) { } Empty packages don't seem to be explicitly forbidden, but they don't serve a purpose with device properties. Instead, if packages without any properties or children are skipped then this empty package is not written and the added child property can refer to another property that is already defined. This allows creating property references to existing tables, which can save duplication and namespace collision issues with nested properties. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-29arch/x86/acpigen: Constify fieldlist parameter to acpigen_write_fieldFurquan Shaikh
acpigen_write_field() does not need to modify the fieldlist parameter. Thus, this change makes this parameter as const. Change-Id: I94688913cee8948f42ae5e184f2d24264876648d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40784 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29arch/x86/acpigen: Add helpers for Store() and If (Lequal (...))Furquan Shaikh
This change adds the following acpigen helpers: a. acpigen_write_store_op_to_namestr: This generates ACPI code for storing an ACPI OP to name string b. acpigen_write_if_lequal_namestr_int: This generates ACPI code for checking if operand1 and operand2 are equal where operand1 is namestring and operand2 is an integer. Change-Id: I84c158361c0725c2927f06be35391e61f627a453 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40783 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29arch/x86: Implement RESET_VECTOR_IN_RAMFelix Held
Add support for devices with the reset vector pointing into DRAM. This is a specific implementation that assumes a paradigm of AMD Family 17h (a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's state appears to software like other designs, and then the actual physical addressing becomes recognizable. These systems cannot implement cache-as-RAM as in more traditional x86 products. Therefore instead of reusing CAR names and variables, a substitute called "earlyram" is introduced. This change makes adjustments to CAR-aware files accordingly. Enable NO_XIP_EARLY_STAGES. The first stage is already in DRAM, and running subsequent stages as XIP in the boot device would reduce performance. Finally, add a new early_ram.ld linker file. Because all stages run in DRAM, they can be linked with their .data and .bss as normal, i.e. they don't need to rely on storage available only at a fixed location like CAR systems. The primary purpose of the early_ram.ld is to provide consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc. across stages until cbmem is brought online. BUG=b:147042464 TEST=Build for trembyle, and boot to ramstage. $ objdump -h cbfs/fallback/bootblock.debug Idx ,Name ,Size ,VMA ,LMA ,File off Algn 0 ,.text ,000074d0 ,08076000 ,08076000 ,00001000 2**12 1 ,.data ,00000038 ,0807d4d0 ,0807d4d0 ,000084d0 2**2 2 ,.bss ,00000048 ,0807d508 ,0807d508 ,00008508 2**2 3 ,.stack ,00000800 ,0807daf0 ,0807daf0 ,00000000 2**0 4 ,.persistent ,00001cfa ,0807e2f0 ,0807e2f0 ,00000000 2**0 5 ,.reset ,00000010 ,0807fff0 ,0807fff0 ,0000aff0 2**0 6 ,.debug_info ,0002659c ,00000000 ,00000000 ,0000b000 2**0 7 ,.debug_abbrev ,000074a2 ,00000000 ,00000000 ,0003159c 2**0 8 ,.debug_aranges,00000dd0 ,00000000 ,00000000 ,00038a40 2**3 9 ,.debug_line ,0000ad65 ,00000000 ,00000000 ,00039810 2**0 10 ,.debug_str ,00009655 ,00000000 ,00000000 ,00044575 2**0 11 ,.debug_loc ,0000b7ce ,00000000 ,00000000 ,0004dbca 2**0 12 ,.debug_ranges ,000029c0 ,00000000 ,00000000 ,00059398 2**3 Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28arch/x86/acpi_device: Constify struct device * parameter to UID functionsFurquan Shaikh
acpi_device_uid() and acpi_device_write_uid() do not need to make changes to the device structure. Thus, this change marks struct device * parameter to these functions as const. Change-Id: I3755223766c78f93c57ac80caf392985cfd5c5e5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40702 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28arch/x86/acpi_device: Add a helper function to write PCI deviceFurquan Shaikh
This change adds a helper function to write a PCI device with _ADR and _STA defined for it. BUG=b:153858769 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I932af917d91198876fe8e90af9bb7a2531bd8960 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40674 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27arch/x86/acpigen: Add helpers for generating _ADRFurquan Shaikh
This change adds the following helpers: acpigen_write_ADR: Generates _ADR object using provided 64-bit address acpigen_write_ADR_pci_devfn: Generates _ADR object for PCI bus device using devfn as input. acpigen_write_ADR_pci_device: Generates _ADR object for PCI bus device using struct device * as input. BUG=b:153858769 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I139dfc30aa7db303c1e8bd4a8f9ee0933a60139b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40670 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-22arch/x86/acpigen_ps2_keybd: Add JP and UK specific keymapsRajat Jain
Add keymaps for keys that are not present in US keyboards. Change-Id: I1ad4c483e81438456533b4c071a4a56cbee88f9c Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20arch/x86/acpi: Add code to generate ACPI for PS2 keyboardsRajat Jain
Add new file to generate ACPI _DSD code for PS2 keyboards. The following 2 device properties are generated as needed: function-row-phymap: A list of ordered scancodes for function row. linux,keymap: Symantically, this is an array of "scancode,keycode" tuple entries. Each entry teaches linux the keycode corresponding to a scancode. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I5ee05173106a125793e91c263610731543c85472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-20drivers/pc80/rtc: Reorganize prototypesKyösti Mälkki
Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15cpu/x86/acpi: Add assignments to ACPI_Sn enumsMarshall Dawson
Explicitly assign numerical values to the enumerated sleep state values. BUG=b:153854742 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I1de2e7f65a2dc3f8a9a1c5fd83d164871a4a2b96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13acpi: Bump MADT to revision 3Patrick Rudolph
Add structs and methods for revision 3. Change-Id: Ida75f530551ad2b8b20ce7fdeffb3befc51296bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-06arch/x86/acpi: add definitions for IVHD type 11hMichał Żygowski
Add definitions of I/O Virtualization Hardware Definition Block type 11h structures for ACPI I/O Virtualization Reporting Structure generation. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I698ac6f6a2e0bc5736fbb14ef583bbe031baee28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40041 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31arch/x86/tables: Move max ACPI table size to KconfigDuncan Laurie
The maximum ACPI table size is currently hardcoded to 144 KiB. When using QEMU with TPM enabled there is ~200 KiB of ACPI tables returned by the fw_cfg interface, so in order to allow this to be overridden by a mainboard move it to Kconfig. This is seen when using a TPM with qemu as it will hang when processing the fw_cfg tables. qemu-system-x86_64 \ -machine q35 -enable-kvm -vga virtio -serial stdio \ -drive 'id=hd,file=disk.bin' -bios coreboot.rom \ -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \ -tpmdev 'emulator,id=tpm0,chardev=swtpm' \ -device 'tpm-tis,tpmdev=tpm0' Change-Id: Ib5baa8fe12cb9027a340875f1ccf5fef6f9460bd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31security/vboot: Decouple measured boot from verified bootBill XIE
Currently, those who want to use measured boot implemented within vboot should enable verified boot first, along with sections such as GBB and RW slots defined with manually written fmd files, even if they do not actually want to verify anything. As discussed in CB:34977, measured boot should be decoupled from verified boot and make them two fully independent options. Crypto routines necessary for measurement could be reused, and TPM and CRTM init should be done somewhere other than vboot_logic_executed() if verified boot is not enabled. In this revision, only TCPA log is initialized during bootblock. Before TPM gets set up, digests are not measured into tpm immediately, but cached in TCPA log, and measured into determined PCRs right after TPM is up. This change allows those who do not want to use the verified boot scheme implemented by vboot as well as its requirement of a more complex partition scheme designed for chromeos to make use of the measured boot functionality implemented within vboot library to measure the boot process. TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook(). Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-03-25arch/x86: Add Kconfig option for 2nd VGA BIOS imageMartin Roth
Picasso and Dali need different video bioses even though they use the same code in most other places. The Kconfig symbol names are changed from the downstream commit to make them more consistent with current coreboot code. BUG=b:145817712 TEST=Build Dali vBIOS into the coreboot image Change-Id: Ide0d061fda0abc78a74ddf97ba81fc3cf2b02e4f Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1956534 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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