summaryrefslogtreecommitdiff
path: root/src/arch/x86
AgeCommit message (Collapse)Author
2015-03-21x86: fix romstage_null.debug link w/o --gc-sectionsAaron Durbin
When adding gargabe collection to x86 the --gc-sections flags was inadvertently missed when linking romstage_null.debug. Fix this omission. Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8850 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-20loaders: add program_loading.h header fileAaron Durbin
Instead of two headers for payload and ramstage loading combine the 2 files into one. This also allows for easier refactoring by keeping header files consistent. Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8708 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17arch/x86/Kconfig: Add license headerStefan Reinauer
Add license header with copyright of the original authors. Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8691 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17coreboot: x86: enable gc-sectionsAaron Durbin
Garbage collected sections allow for trimming the size of the binaries as well as allowing for not needing to config off unused functions. To that end, on a rambi build the following differences are observed: $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf) --- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500 +++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500 @@ -6,9 +6,9 @@ There are 4 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0 - LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0 - LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0 - LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0 + LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0 + LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0 + LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0 Section to Segment mapping: Segment Sections... $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf) --- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500 +++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500 @@ -5,8 +5,8 @@ There are 1 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E 0x10 + LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E 0x10 Section to Segment mapping: Segment Sections... - 00 .rom .text + 00 .rom The following warnings needed to be applied to CFLAGS_common because for some reason gcc was miraculously emitting the warnings with the unrelated *-sections options: -Wno-unused-but-set-variable Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8188 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10x86: simplify early_variables.h headerAaron Durbin
The CAR macros and the associated functions are only employed under the following conditions: - chipsets which have CAR - compilation during romstage Therefore clean up the build-time conditionals to use those 2 constructs. Change-Id: I2b923feeb68f2b964c5ac57e11391313d9c8ffc5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8634 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-09AMD fam10: Drop PCI_BUS_SEGN_BITSKyösti Mälkki
All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04Add stage information to coreboot bannerStefan Reinauer
As a convenience, print the actual stage name when entering a stage. Also unify the banner between bootblock / romstage and ramstage. No reason for two different occurences. Instead of this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting... you will see this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting... Roughly based on: https://chromium-review.googlesource.com/199671 Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8578 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23Remove */cpu/amd/agesa/* from excluded illegal globals fileDave Frodin
The change in commit 5636237 allows */cpu/amd/agesa/* to be removed. TEST: Booted the amd/parmer board. Change-Id: I8d2d2639f8e5f3b1dd58be96be98db0eff7b268f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8505 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16nvram: Add option to reset NVRAM to default parameters on every bootTimothy Pearson
In specific configurations, such as homogeneous supercomputing systems, changeable NVRAM parameters are more of a liability than a useful tool. This patch allows a coreboot image to be compiled that will always set the NVRAM parameters to their default values, reducing maintainance overhead on large clusters. Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8446 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14arch/x86/boot/tables.c: Remove unused variable assignment to `rom_table_end`Paul Menzel
Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-09Get rid of .car.global_data warnings for GCC buildMartin Roth
The "used" attribute was added in commit 27cf2472 which caused these warnings to start appearing when using the standard coreboot GCC toolchain: {standard input}: Assembler messages: {standard input}:96: Warning: ignoring changed section type for .car.global_data {standard input}:96: Warning: ignoring changed section attributes for .car.global_data The # at the end of the section name causes the assembler to ignore everything following the name. I verified that the resulting binaries are the same with and without the #. Change-Id: Iaac8042533842ed887f33895f083b613a18f496a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8301 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-02src/arch/*/include/stdint.h: Provide definitions for bool typeAlexandru Gagniuc
Although bool normally belongs in stdbool.h, for our use cases, providing these definitions in stdint.h is acceptable. Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8279 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INITKyösti Mälkki
We can now create CBMEM with dynamic allocation even if CBMEM location is resolved late in ramstage. Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7861 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Tidy up CAR migrationKyösti Mälkki
Move the CAR migration call to arch -specific part of CBMEM init, it is truly a x86 specific thing. Change-Id: I715417e54f197b8745e0670d6b900a5660178141 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7860 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Tag chipsets with LATE_CBMEM_INITKyösti Mälkki
In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7850 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Add timestamp_reinit()Kyösti Mälkki
This avoids the need for separate timestamp_reinit() calls made via CAR_MIGRATE() that is not implemented for ARM. Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8033 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM console: Fix CAR migration stepKyösti Mälkki
With the change it becomes irrelevant if memcpy() car.global_data or cbmemc_reinit() is done first. Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8032 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Implement cbmem_run_init_hooks() stubKyösti Mälkki
Until we completely can unify early_variables, use these to handle CBMEM update hooks for both romstage and ramstage. For x86, CAR_MIGRATE serves the purpose of romstage hooks. Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7876 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-10ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10ACPI: Prepare for HAVE_ACPI_RESUME changesKyösti Mälkki
Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8186 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09misc: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. Instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the generic code pieces to use printk() on all non-ROMCC boards. Our two remaining ROMCC boards are fixed up in this commit: bifferos/bifferboard and dmp/vortex86ex. Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8115 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-04atomic.h: Fix doxygen errorsMartin Roth
- @v & @i need to be @param v & @param i - add the @file command Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8075 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-31arch/x86: Declare GDT symbols and move_gdt()Kyösti Mälkki
We relocate GDT to CBMEM, this can be done late in ramstage. Note: We currently do this for BSP CPU only. Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7858 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30CBMEM: Always build for x86 romstageKyösti Mälkki
Always build CBMEM for romstage, even for boards that will not use it. We further restrict car_migrate_variables() runs to non-ROMCC boards without BROKEN_CAR_MIGRATE. This fixes regression of commit 71b21455 that broke CBMEM console support for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME. Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7877 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPIKyösti Mälkki
After relocation the weak symbols are no longer NULL. Always have empty stub function defined. Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7955 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-09x86: provide symmetry between arm for cache_sync_instructions()Aaron Durbin
The arm architecture currently exports cache_sync_instructions() in <arch/cache.h>. In order for rmodule loading to work on arm architectures the cache_sync_instructions() needs to be called to sequence the instruction cache. To avoid sprinkling #ifdefs around just add an empty cache_sync_instructions() definition. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built and booted nyan and rambi. Original-Change-Id: I1a969757fffe0ca92754a0d953ba3630810556e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/191551 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit fda20947b928ee761d5ed15e414636af419970a6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e8ca12e1d82ccedf1ff9851ae3c5c80cda2dd5f Reviewed-on: http://review.coreboot.org/7710 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-05x86: Update the check for Forbidden global variablesFurquan Shaikh
Add a section .illegal_globals to romstage and check that the section does not contain any variables while creating romstage. [pg: Handle individual AGESA special cases in the linker script instead of whitelisting everything remotely AGESA related in the Makefile.] Change-Id: I866681f51a44bc21770d32995c281b556a90c153 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7306 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02build system: remove ROMSTAGE_ELF variablePatrick Georgi
No need to keep that just because x86 has one extra linking step. Change-Id: Iffdbf64e0613f89070ed0dfb009379f5ca0bd3c1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7611 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30Unify remaining binutils invocationsPatrick Georgi
No need to pass calls through gcc in one case and directly to binutils in another. Just always call binutils. Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7610 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-27Make acpi_fill_dmar into parameterVladimir Serbinenko
Change-Id: I5e237cb7acbf47b2c8a4cd725ee8e16e422e3b17 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7371 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-25build system: unify linker use across gcc and clangPatrick Georgi
Let's just call ld directly for gcc, too. Change-Id: I305eb92ed0d21b098134a7eb5a9f9fe3b126aeea Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7553 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-25build system: use a single variable name for compiler runtimesPatrick Georgi
We build with either gcc or clang, no need to keep both around Change-Id: I9af2cc7636bdc791a68ba8ed6e7c5a81973c5dfd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7552 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-22acpigen: Use implicit length patching in acpigen.cVladimir Serbinenko
Change-Id: I0aa333911edabd5c9f844a2171dfa9fafe7de785 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7364 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
As build.h is an auto-generated file it was necessary to add it as an explicit prerequisite in the Makefiles. When this was forgotten abuild would sometimes fail with following error: fatal error: build.h: No such file or directory Fix this error by compiling version.c into all stages. Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7510 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19acpigen: Use implicit length patching in acpigen_write_resourcetemplate_footerVladimir Serbinenko
Change-Id: Ic177720b074fed13a17454dcb6765ac298365624 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7366 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19acpigen: Add and use acpigen_write_device.Vladimir Serbinenko
The sequence of bytes to create a method is used several times in codebase. Put it into a function with logical arguments rather than duplicating magic bytes everywhere. Change-Id: I2c33fa403832eb1cfadfbf8d9adef5b63fb9cb24 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7348 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-19acpigen: Add and use acpigen_write_method.Vladimir Serbinenko
The sequence of bytes to create a method is used several times in codebase. Put it into a function with logical arguments rather than duplicating magic bytes everywhere. Change-Id: I0e55d8dc7d5e8e92a521c7a83117c470d0614008 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7347 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19console: Isolate console_init() for ROMCCKyösti Mälkki
Change-Id: I623643834fb1c6af166a851fec7e31447944f0b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7509 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 08:05:59 +0000