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2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-05arch/x86/include/stdint: Fix PRIu64Patrick Rudolph
We alwas define uint64_t as unsigned long long, even on x86_64. Fix PRIu64 to match the definition of the datatype, to prevent compilation errors when compiling for x86_64. Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-04acpi_pld: Make it easier to define the ACPI USB device groupsDuncan Laurie
The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29arch/acpi.h: Add some update to version 6.2aElyes HAOUAS
Some tables updated to comply with ACPI version 6.2a. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-29arch/x86/acpigen.c: Add a method to notify all CPU coresArthur Heymans
Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29arch/x86/Makefile.inc: Fix typoPatrick Rudolph
Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23arch/x86: drop special case cbfs locatorPatrick Georgi
CBFS used to have a special region for the x86 bootblock, which also contained a pointer to a CBFS master header, which describes the layout of the CBFS. Since we adopted other architectures, we got rid of the bootblock region as a separate entity and add the x86 bootblock as a CBFS file now. The master header still exists for compatibility with old cbfstool versions, but it's neatly wrapped in either the bootblock file or in a file carefully crafted at the right location (on all other architectures). All the layout information we need is now available from FMAP, a core part of a contemporary coreboot image, even on x86, so we can just use the generic master header locator in src/lib/cbfs.c and get rid of the special version. Among the advantages: the x86 header locator reduced the size of the CBFS by 64 bytes assuming that there's the bootblock region of at least that size - this breaks assumptions elsewhere (eg. when walking CBFS in cbfs_boot_locate() because the last file, the bootblock, will exceed the CBFS region as seen by coreboot (since it's CBFS - 64bytes). TEST=emulation/qemu-q35 still boots Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23src/arch/x86/acpi.c: Create log area and extend TPM2 tableMichał Żygowski
According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-23soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-14mb/emulation/qemu-i440fx|q35: Fix stack sizePatrick Rudolph
Current implementation works by luck as DCACHE area is actually RAM and stack can grow and use that RAM outside of the area. * Set DCACHE_BSP_STACK_SIZE to 0x4000. * Add an assert to make sure it is set to a sane value on all platforms. Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29611 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATIONFurquan Shaikh
Change 76ab2b7 ("arch/x86: allow global .bss objects without CAR_GLOBAL") allowed use of global .bss objects and hence moved around the macros resulting in car_active returning 0 even for those boards where CAR is actually active but do not require global migration. This resulted in boards getting stuck when doing a reset in verstage because the code flow incorrectly assumed that there was no CAR active and hence triggered a cache invalidate. This change fixes the above issue by returning 1 for car_active if ENV_CACHE_AS_RAM is set even if global migration is not required. BUG=b:109717603 TEST=Verified that board reset does not trigger cache invalidate in verstage and does not result in board hang. Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-09include/program_loading: Add POSTCAR prog typePhilipp Deppenwiese
Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-08toolchain: Add POSTCAR as a stage we have a toolchain forPatrick Georgi
Fixes building vb2lib for postcar. Since postcar is an x86ism, add the Kconfig options only for x86. Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29395 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-06x86/acpi.c: Be more verbose when finding the wakeup vectorAngel Pons
Since S3 resume sometimes breaks when trying to find the wakeup vector, it is useful to log whether it errors or not. Since it is an error, print it as such. Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01arch/x86: clarify raw CAR_GLOBAL access guardsAaron Durbin
Romstage is where DRAM comes online. Therefore, allow raw CAR_GLOBAL object access in all cache-as-ram stages that are not romstage. In practice, this should be a nop. However, the explicit check for romstage is clearer. Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-01arch/x86: allow global .bss objects without CAR_GLOBALAaron Durbin
For platforms utilizing CONFIG_NO_CAR_GLOBAL_MIGRATION there's no need to automatically migrate globals. Because of this it's possible to automatically allow for uninitialized global variables which reside in the .bss section without needing to decorate those objects with CAR_GLOBAL. Change-Id: Icae806fecd936ed2ebf0c13d30ffa07c77a95150 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-26arch/x86/acpi: Add TPM2 table supportPhilipp Deppenwiese
* Distinguish between TPM 1.2 and 2.0 ACPI table support * Add TPM2 table support for TIS interface only Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/29181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23acpi_device: Refine ACPI_IRQ_* macrosFurquan Shaikh
This change does the following: 1. Adds a helper macro ACPI_IRQ_CFG that can be used by all other ACPI_IRQ* macros to initialize acpi_irq structure. 2. Provides ACPI_IRQ_WAKE* versions to allow board to define an irq as wake capable. BUG=b:117553222 Change-Id: Ic53c6019527bbd270806897247f547178cd1ad3c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-22arch/x86: Implement common CF9 resetNico Huber
It's very common across many x86 silicon vendors, so place it in `arch/x86/`. Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-17arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer
Add punctuation and fix a typo. Change-Id: Ic61c665f7e2daefb50b478a1710ea66c8a88235a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04arch/x86: Make mb/romstage.c optionalRizwan Qureshi
Currently src/mainboard/*/romstage.c is mandatory for compiling, this makes having the file present even though there is nothing to initialize in romstage on the mainboard side. Eliminate the need to have empty romstage.c files using the wildcard function. BUG=None BRANCH=None TEST= build cannonlake_rvp after removing the romstage.c file. Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-09-16acpi: Call acpi_gen_writeSTA by status from device treeHung-Te Lin
The device tree now supports 'hidden' and the status can be found in `struct device.hidden`. A new acpi_device_status() will return the expected setting of STA from a `struct device`. BUG=b:72200466 BRANCH=eve TEST=Builds and boots properly on device eve Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28567 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706Richard Spiegel
There are 8 possible BERT context errors, with table ctx_names being a table to print their names. Thus the table is supposed to have 8 elements, and indeed it has 8 lines... but some lines are missing commas, and when compiling it becomes a 5 element table. Add the commas at the appropriate places. BUG=b:115719190 TEST=none. Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-09-14arch/x86/acpigen: Fix comment in _ROM method generatorJonathan Neuschäfer
Commit 24462e6507 ("x86/acpigen: Fix ACPI _ROM method") changed the code to generate a serialized method, but didn't adjust the comment. Change-Id: Ie7dbaff13d36f31e9d627609d0f74a4e9fa5a1e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-07x86/acpi: Add BERT tableMarshall Dawson
Create a structure for the Boot Error Record Table, and a generic table generator function. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07x86/acpi: Add BERT to the revision tableMarshall Dawson
Add the proper table revision level for the Boot Error Record Table. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28471 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07arch/x86: Add BERT region support functionsMarshall Dawson
Add code for generating the region pointed to in an ACPI Boot Error Record Table. The BERT region must be reported as Reserved to the OSPM, so this code calls out to a system-specific region locator. cbmem is reported as type 16 and is not usable for the BERT region. Events reported via BERT are Generic Error Data, and are constructed as follows (see ACPI and UEFI specs for reference): * Each event begins with a Generic Error Status Block, which may contain zero or more Generic Data Entries * Each Generic Data Entry is identifiable by its Section Type field, and the data structures associated are also in the UEFI spec. * The GUIDs are listed in the Section Type field of the CPER Section Descriptor structure. BERT doesn't use this structure but simply uses its GUIDs. * Data structures used in the Generic Data Entry are named as Error Sections in the UEFI spec. * Some sections may optionally include a variable number of additional structures, e.g. an IA32/X64 processor error can report error information as well as machine contexts. It is worth noting that the Linux kernel (as of v4.4) does not attempt to parse IA32/X64 sections, and opts to hexdump them instead. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28470 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06x86/acpi: Add APEI definitionsMarshall Dawson
Add ACPI Platform Error Interfaces definitions that will be used for building a BERT table region in a subsequent patch. Two tables are defined: the Generic Error Status Block, Generic Error Data Entry. For reference, see the ACPI specification 6.2-A tables 381 and 382. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-05arch/x86/Makefile: include dependencies for romcc bootblockNico Huber
We already explicitly generated a dependencies file for the romcc bootblock. Though, as it has its own rule and isn't registered to any of our object-file classes, the dependencies file wasn't included automatically. Change-Id: I441cf229312dff82f377dcb594939fb85c441eed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/28442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27x86/acpi: Update MADT table versionMarc Jones
Update the MADT table version to sync with the FADT table version. All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0 and the MADT should be set to match. This error was found by running FWTS: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27x86/acpi: Add ACPI table revision functionMarc Jones
Use a single function to set ACPI table versions. This allows us to keep revisions synced to the correct levels for coreboot. This is a partial fix for the bug: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28276 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22acpi: remove CBMEM_ID_ACPI_GNVS_PTR entryJoel Kitching
Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. TEST=Compile and run on Eve Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Reviewed-on: https://review.coreboot.org/28189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-17x86/acpigen: Fix ACPI _ROM methodMarc Jones
Fix the following Error: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 142 Line | AML source -------------------------------------------------------------------------------- 00139| 00140| Scope (\_SB.PCI0.IGFX) 00141| { 00142| Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00143| { 00144| OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00) 00145| Field (ROMS, AnyAcc, NoLock, Preserve) ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. Use the acpigen_write_method_serialized() to correct the error. BUG=b:112476331 TEST=Run FWTS. Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-17arch/x86/acpigen: add methods for cppcMatt Delco
This change adds 2 methods for Conginuous Performance Control that was added in ACPI 5.0 and expanded twice in later versions. One function will create a global table based on a provided struct, while the other function is used to add a _CPC method in each processor object. Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15arch/x86/acpigen: refactor calls to acpigen_write_registerMatt Delco
All of the callers to acpigen_write_register() also make calls to acpigen_write_resourcetemplate_[header|footer](). This change introduces acpigen_write_register_resource() to unify all of those trio of calls into one. I also made the input parameter const. Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27672 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14cbmem: rename vdat to chromeos_acpiJoel Kitching
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-09arch/x86/tables.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure arch_write_tables, the pointer "rom_table_end" is updated every time a table is created. However, after creating last table, pointer rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/arch: Fix typoElyes HAOUAS
Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09arch/x86/exception.c: Remove double initializationRichard Spiegel
In procedure exception_init(), structure pointer gates is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27948 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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