summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
2018-11-05riscv: add support to block smp in each stageXiang Wang
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-11-01arch/x86: clarify raw CAR_GLOBAL access guardsAaron Durbin
2018-11-01arch/x86: allow global .bss objects without CAR_GLOBALAaron Durbin
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30riscv: simplify timer interrupt handlingPhilipp Hug
2018-10-30src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug
2018-10-26arch/x86/acpi: Add TPM2 table supportPhilipp Deppenwiese
2018-10-25selfboot: create selfboot_check function, remove check paramRonald G. Minnich
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-23acpi_device: Refine ACPI_IRQ_* macrosFurquan Shaikh
2018-10-22arch/x86: Implement common CF9 resetNico Huber
2018-10-17arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer
2018-10-12libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-06arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer
2018-10-04arch/x86: Make mb/romstage.c optionalRizwan Qureshi
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
2018-09-26arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer
2018-09-21arch/{mips,power8}/include/arch: Don't use device_tElyes HAOUAS
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
2018-09-19arch/arm/include/armv7/arch: Remove dead codeElyes HAOUAS
2018-09-16acpi: Call acpi_gen_writeSTA by status from device treeHung-Te Lin
2018-09-16riscv: don't write to mstatus.XSXiang Wang
2018-09-15arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706Richard Spiegel
2018-09-15arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer
2018-09-14arch/x86/acpigen: Fix comment in _ROM method generatorJonathan Neuschäfer
2018-09-14arch/riscv: Only execute on hart 0 for nowPhilipp Hug
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14arch/riscv: add missing endian.h header to io.hPhilipp Hug
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-07x86/acpi: Add BERT tableMarshall Dawson
2018-09-07x86/acpi: Add BERT to the revision tableMarshall Dawson
2018-09-07arch/x86: Add BERT region support functionsMarshall Dawson
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
2018-09-06x86/acpi: Add APEI definitionsMarshall Dawson
2018-09-05arch/x86/Makefile: include dependencies for romcc bootblockNico Huber
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
2018-09-04riscv: add spin lock supportXiang Wang
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu